926 resultados para Capacitor voltage equalization


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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

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Ca(Zr0.05Ti0.95)O-3 (CZT) thin films were grown on Pt(1 1 1)/Ti/SiO2/Si(1 0 0) substrates by the soft chemical method. The films were deposited from spin-coating technique and annealed at 928 K for 4 h under oxygen atmosphere. CZT films present orthorhombic structure with a crack free and granular microstructure. Atomic force microscopy and field-emission scanning electron microscopy showed that CZT present grains with about 47 nm and thickness about 450 nm. Dielectric constant and dielectric loss of the films was approximately 210 at 100 kHz and 0.032 at 1 MHz. The Au/CZT/Pt capacitor shows a hysteresis loop with remnant polarization of 2.5 mu C/cm(2), and coercive field of 18 kV/cm, at an applied voltage of 6 V. The leakage current density was about 4.6 x 10(-8) A/cm(2) at 3 V. Dielectric constant-voltage curve is located at zero bias field suggesting the absence of internal electric fields. (c) 2006 Elsevier B.V. All rights reserved.

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A description is given of the nonohmic behavior obtained in (SnxTi1-x)O-2-based systems. A matrix founded on (SnxTi1-x)O-2-based systems doped with Nb2O5 leads to a low-voltage varistor system with nonlinear coefficient values of similar to9. The presence of the back-to-back Schottky-type barrier is observed based on the voltage dependence of the capacitance. When doped with CoO, the (SnxTi1-x)O(2)(.)based system presents higher nonlinear coefficient values (>30) than does the SnO2-based varistor system.

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The phenomenon of electrical degradation in ZnO varistors was studied by application of high-intensity current pulses. A wave shape of 8 X 20-mu-s and rectangular waves of 1 and 2 ms were used. The degradation was estimated by reference electric-field variation and by Schottky voltage barrier deformation. The results showed that current pulses reduce both the height and the width of the barrier voltage. It was also observed that the donor density N(d) did not change but the surface states density N(s) decreased with degradation.

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An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

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BaBi2Ta2O9 thin films having a layered structure were fabricated by metalorganic solution deposition technique. The films exhibited good structural, dielectric, and insulating properties. The room temperature resistivity was found to be in the range of 10(12)-10(14) Omega cm up to 4 V corresponding to a field of 200 kV/cm across the capacitor for films annealed in the temperature range of 500-700 degrees C. The current-voltage (I-V) characteristics as a function of thickness for films annealed at 700 degrees C for 1 h, indicated bulk limited conduction and the log(I) vs V-1/2 characteristics suggested a space-charge-limited conduction mechanism. The capacitance-voltage measurements on films in a metal-insulator-semiconductor configuration indicated good Si/BaBi2Ta2O9 interface characteristics and a SiO2 thickness of similar to 5 nm was measured and calculated. (C) 1999 American Institute of Physics. [S0003-6951(99)00830-X].

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A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

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High critical temperature superconductors are evolving from a scientific research subject into large-scale application devices. In order to meet this development demand they must withstand high current capacity under mechanical loads arising from thermal contraction during cooling from room temperature down to operating temperature (usually 77 K) and due to the electromagnetic forces generated by the current and the induced magnetic field. Among the HTS materials, the Bi2Sr2Ca2Cu3Ox, compound imbedded in an Ag/AgMg sheath has shown the best results in terms of critical current at 77 K and tolerance against mechanical strain. Aiming to evaluate the influence of thermal stress induced by a number of thermal shock cycles we have evaluated the V-I characteristic curves of samples mounted onto semicircular holders with different curvature radius (9.75 to 44.5 mm). The most deformed sample (epsilon = 1.08%) showed the largest reduction of critical current (40%) compared to the undeformed sample and the highest sensitivity to thermal stress (I-c/I-c0 = 0.5). The V-I characteristic curves were also fitted by a potential curve displaying n-exponents varying from 20 down to 10 between the initial and last thermal shock cycle.

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ZnO seed particles and Cr2O3 were used in this study to control the microstructure of ZnO varistors. The seed particles were prepared by adding 1.0 mol % BaO to ZnO. The powder was then calcined at 800-degrees-C for 2 h, pressed into pellets and sintered at 1400-degrees-C for 8 h. The sintered ZnO was ground and the BaO eliminated by washing in water. The remaining ZnO powder was classified into a size fraction ranging from 38 to 149 mum. The addition of a small amount (1 weight %) ZnO seed grains produces varistors with low breakdown voltages (7.6 V/mm) and an alpha coefficient of approximately 10. The addition of Cr2O3 stabilizes the spinel phase yielding a more homogeneous microstructure, but degraded electrical behaviour of the ZnO varistor.

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Composites polymer-ceramic using castor oil-based polyurethane (PU) as non-ferroelectric matrix and Lead Zirconate Titanate (PZT) as ceramic powder have been prepared at thin films form by spin coating. The samples are poled by appropriated electric field to show piezo and pyroelectric activity. The pyroelectric coefficient p(T) at 343 K is obtained to be equal 5.8 X 10(-5) C m(-2) K-1 for a composite with 32 vol.% of ceramic. The figure of merit of this composite is six times higher than of PZT ceramic. The voltage responsivity of the pyroelectric is reduced when the thickness of the sample increases. It was used modulated white light as radiation source to excite the sensor film. The electric signal of the sensor decreases with the light modulation frequency by 1/f. (C) 1999 Elsevier B.V. S.A. All rights reserved.

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The J(1)...J(3) is a recent optical method for linear readout of dynamic phase modulation index in homodyne interferometers. In this work, the J(1)... J(3) method is applied to measure voltage in an optical voltage sensor. Based on the classical J(1)...J(4) method, the J(1)... J(3) technique shows to be more stable to phase drift and simpler for implementation than the original one. The sensor dynamic range is enhanced. The agreement between theoretical and experimental results, based on 1/f noise, is demonstrated.

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A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.