ℓasso MPC: Smart regulation of over-actuated systems

In this paper, a novel MPC strategy is proposed, and referred to as asso MPC. The new paradigm features an 1-regularised least squares loss function, in which the control error variance competes with the sum of input channels magnitude (or slew rate) over the whole horizon length. This cost choice is motivated by the successful development of LASSO theory in signal processing and machine learning. In the latter fields, sum-of-norms regularisation have shown a strong capability to provide robust and sparse solutions for system identification and feature selection. In this paper, a discrete-time dual-mode asso MPC is formulated, and its stability is proven by application of standard MPC arguments. The controller is then tested for the problem of ship course keeping and roll reduction with rudder and fins, in a directional stochastic sea. Simulations show the asso MPC to inherit positive features from its corresponding regressor: extreme reduction of decision variables' magnitude, namely, actuators' magnitude (or variations), with a finite energy error, being particularly promising for over-actuated systems. © 2012 AACC American Automatic Control Council).

An integrated service-device-technology roadmap for smart city development

Firms and other organizations use Technology Roadmapping (TRM) extensively as a framework for supporting research and development of future technologies and products that could sustain a competitive advantage. While the importance of technology strategy has received more attention in recent years, few research studies have examined how roadmapping processes are used to explore the potential convergence of products and services that may be developed in the future. The aim of this paper is to introduce an integrated roadmapping process for services, devices and technologies capable of implementing a smart city development R&D project in Korea. The paper applies a QFD (Quality Function Deployment) method to establish interconnections between services and devices, and between devices and technologies. The method is illustrated by a detailed case study, which shows how different types of roadmap can be coordinated with each other to produce a clear representation of the technological changes and uncertainties associated with the strategic planning of complex innovations. © 2012 Elsevier Inc.

Active control of normal shock wave/turbulent boundary layer interaction using "Smart" piezoelectric flap actuators

This paper looks at active control of the normal shock wave/turbulent boundary layer interaction (SBLI) using smart flap actuators. The actuators are manufactured by bonding piezoelectric material to an inert substrate to control the bleed/suction rate through a plenum chamber. The cavity provides communication of signals across the shock, allowing rapid thickening of the boundary layer approaching the shock, which splits into a series of weaker shocks forming a lambda shock foot, reducing wave drag. Active control allows optimum control of the interaction, as it would be capable of positioning the control region around the original shock position and control the rate of mass transfer. © 2004 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Lifetime distribution of spontaneous emission from line antennas in two-dimensional quasi-periodic photonic crystals

We investigate the lifetime distribution functions of spontaneous emission from line antennas embedded in finite-size two-dimensional 12-fold quasi-periodic photonic crystals. Our calculations indicate that two-dimensional quasi-periodic crystals lead to the coexistence of both accelerated and inhibited decay processes. The decay behaviors of line antennas are drastically changed as the locations of the antennas are varied from the center to the edge in quasi-periodic photonic crystals and the location of transition frequency is varied.

Spontaneous emission lifetime distribution of infinite line antennas in two-dimensional photonic crystals with finite size

The authors calculate the lifetime distribution functions of spontaneous emission from infinite line antennas embedded in two-dimensional disordered photonic crystals with finite size. The calculations indicate the coexistence of both accelerated and inhibited decay processes in disordered photonic crystals with finite size. The decay behavior of the spontaneous emission from infinite line antennas changes significantly by varying factors such as the line antennas' positions in the disordered photonic crystal, the shape of the crystal, the filling fraction, and the dielectric constant. Moreover, the authors analyze the effect of the degree of disorder on spontaneous emission. (c) 2007 American Institute of Physics.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

an improved smart card based password authentication scheme with provable security

Password authentication has been adopted as one of the most commonly used solutions in network environment to protect resources from unauthorized access. Recently, Lee–Kim–Yoo [S.W. Lee, H.S. Kim, K.Y. Yoo, Improvement of Chien et al.'s remote user authentication scheme using smart cards, Computer Standards & Interfaces 27 (2) (2005) 181–183] and Lee-Chiu [N.Y. Lee, Y.C. Chiu, Improved remote authentication scheme with smart card, Computer Standards & Interfaces 27 (2) (2005) 177–180] respectively proposed a smart card based password authentication scheme. We show that these two schemes are both subject to forgery attacks provided that the information stored in the smart card is disclosed by the adversary. We also propose an improved scheme with formal security proof.

FET ACTIVE SLOTLINE NOTCH ANTENNAS FOR QUASI-OPTICAL POWER COMBINING

A new active antenna structure with applications in quasi-optical power combining is described. The active antenna combines a slotline FET oscillator with a notch antenna. The new structure was successfully used to create both E-plane and H-plane linear arrays as well as a 2-D array. Preliminary results of radiation patterns and the power combining efficiencies of the arrays are discussed.

Multiple Quantum Well SEED Arrays for Flip-Chip Bonding Optoelectronic Smart Pixels

于2010-11-23批量导入

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

Multiple quantum well self electro-optic effect devices for optoelectronic smart pixels

The investigations on GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays for optoelectronic smart pixels are reported. The hybrid integration of GaAs/AlGaAs multiple quantum well devices flip-chip bonding directly over 1 mu m silicon CMOS circuits are demonstrated. The GaAs/AlGaAs multiple quantum well devices are designed for 850nm operation. The measurement results under applied biases show the good optoelectronic characteristics of elements in SEED arrays. The 4x4 optoelectronic crossbar structure consisting of hybrid CMOS-SEED smart pixels have been designed, which could be potentially used in optical interconnects for multiple processors.