Parallel Coupled Micro-Macro Actuators

This thesis presents a new actuator system consisting of a micro-actuator and a macro-actuator coupled in parallel via a compliant transmission. The system is called the Parallel Coupled Micro-Macro Actuator, or PaCMMA. In this system, the micro-actuator is capable of high bandwidth force control due to its low mass and direct-drive connection to the output shaft. The compliant transmission of the macro-actuator reduces the impedance (stiffness) at the output shaft and increases the dynamic range of force. Performance improvement over single actuator systems was expected in force control, impedance control, force distortion and reduction of transient impact forces. A set of quantitative measures is proposed and the actuator system is evaluated against them: Force Control Bandwidth, Position Bandwidth, Dynamic Range, Impact Force, Impedance ("Backdriveability'"), Force Distortion and Force Performance Space. Several theoretical performance limits are derived from the saturation limits of the system. A control law is proposed and control system performance is compared to the theoretical limits. A prototype testbed was built using permanenent magnet motors and an experimental comparison was performed between this actuator concept and two single actuator systems. The following performance was observed: Force bandwidth of 56Hz, Torque Dynamic Range of 800:1, Peak Torque of 1040mNm, Minimum Torque of 1.3mNm. Peak Impact Force was reduced by an order of magnitude. Distortion at small amplitudes was reduced substantially. Backdriven impedance was reduced by 2-3 orders of magnitude. This actuator system shows promise for manipulator design as well as psychophysical tests of human performance.

Concurrent Smalltalk on the Message-Driven Processor

Concurrent Smalltalk is the primary language used for programming the J- Machine, a MIMD message-passing computer containing thousands of 36-bit processors connected by a very low latency network. This thesis describes in detail Concurrent Smalltalk and its implementation on the J-Machine, including the Optimist II global optimizing compiler and Cosmos fine-grain parallel operating system. Quantitative and qualitative results are presented.

ADAM: A Decentralized Parallel Computer Architecture Featuring Fast Thread and Data Migration and a Uniform Hardware Abstraction

The furious pace of Moore's Law is driving computer architecture into a realm where the the speed of light is the dominant factor in system latencies. The number of clock cycles to span a chip are increasing, while the number of bits that can be accessed within a clock cycle is decreasing. Hence, it is becoming more difficult to hide latency. One alternative solution is to reduce latency by migrating threads and data, but the overhead of existing implementations has previously made migration an unserviceable solution so far. I present an architecture, implementation, and mechanisms that reduces the overhead of migration to the point where migration is a viable supplement to other latency hiding mechanisms, such as multithreading. The architecture is abstract, and presents programmers with a simple, uniform fine-grained multithreaded parallel programming model with implicit memory management. In other words, the spatial nature and implementation details (such as the number of processors) of a parallel machine are entirely hidden from the programmer. Compiler writers are encouraged to devise programming languages for the machine that guide a programmer to express their ideas in terms of objects, since objects exhibit an inherent physical locality of data and code. The machine implementation can then leverage this locality to automatically distribute data and threads across the physical machine by using a set of high performance migration mechanisms. An implementation of this architecture could migrate a null thread in 66 cycles -- over a factor of 1000 improvement over previous work. Performance also scales well; the time required to move a typical thread is only 4 to 5 times that of a null thread. Data migration performance is similar, and scales linearly with data block size. Since the performance of the migration mechanism is on par with that of an L2 cache, the implementation simulated in my work has no data caches and relies instead on multithreading and the migration mechanism to hide and reduce access latencies.

Bit-Width Analysis for General Applications

It has been widely known that a significant part of the bits are useless or even unused during the program execution. Bit-width analysis targets at finding the minimum bits needed for each variable in the program, which ensures the execution correctness and resources saving. In this paper, we proposed a static analysis method for bit-widths in general applications, which approximates conservatively at compile time and is independent of runtime conditions. While most related work focus on integer applications, our method is also tailored and applicable to floating point variables, which could be extended to transform floating point number into fixed point numbers together with precision analysis. We used more precise representations for data value ranges of both scalar and array variables. Element level analysis is carried out for arrays. We also suggested an alternative for the standard fixed-point iterations in bi-directional range analysis. These techniques are implemented on the Trimaran compiler structure and tested on a set of benchmarks to show the results.

Exploring Bit-Difference for Approximate KNN Search in High-dimensional Databases

In this paper, we develop a novel index structure to support efficient approximate k-nearest neighbor (KNN) query in high-dimensional databases. In high-dimensional spaces, the computational cost of the distance (e.g., Euclidean distance) between two points contributes a dominant portion of the overall query response time for memory processing. To reduce the distance computation, we first propose a structure (BID) using BIt-Difference to answer approximate KNN query. The BID employs one bit to represent each feature vector of point and the number of bit-difference is used to prune the further points. To facilitate real dataset which is typically skewed, we enhance the BID mechanism with clustering, cluster adapted bitcoder and dimensional weight, named the BID⁺. Extensive experiments are conducted to show that our proposed method yields significant performance advantages over the existing index structures on both real life and synthetic high-dimensional datasets.

On-the-Fly Maintenance of Series-Parallel Relationships in Fork-Join Multithreaded Programs

A key capability of data-race detectors is to determine whether one thread executes logically in parallel with another or whether the threads must operate in series. This paper provides two algorithms, one serial and one parallel, to maintain series-parallel (SP) relationships "on the fly" for fork-join multithreaded programs. The serial SP-order algorithm runs in O(1) amortized time per operation. In contrast, the previously best algorithm requires a time per operation that is proportional to Tarjan’s functional inverse of Ackermann’s function. SP-order employs an order-maintenance data structure that allows us to implement a more efficient "English-Hebrew" labeling scheme than was used in earlier race detectors, which immediately yields an improved determinacy-race detector. In particular, any fork-join program running in T₁ time on a single processor can be checked on the fly for determinacy races in O(T₁) time. Corresponding improved bounds can also be obtained for more sophisticated data-race detectors, for example, those that use locks. By combining SP-order with Feng and Leiserson’s serial SP-bags algorithm, we obtain a parallel SP-maintenance algorithm, called SP-hybrid. Suppose that a fork-join program has n threads, T₁ work, and a critical-path length of T[subscript ∞]. When executed on P processors, we prove that SP-hybrid runs in O((T₁/P + PT[subscript ∞]) lg n) expected time. To understand this bound, consider that the original program obtains linear speed-up over a 1-processor execution when P = O(T₁/T[subscript ∞]). In contrast, SP-hybrid obtains linear speed-up when P = O(√T₁/T[subscript ∞]), but the work is increased by a factor of O(lg n).

Design and Development of 3-DOF Modular Micro Parallel Kinematic Manipulator

This paper presents the research and development of a 3-legged micro Parallel Kinematic Manipulator (PKM) for positioning in micro-machining and assembly operations. The structural characteristics associated with parallel manipulators are evaluated and the PKMs with translational and rotational movements are identified. Based on these identifications, a hybrid 3-UPU (Universal Joint-Prismatic Joint-Universal Joint) parallel manipulator is designed and fabricated. The principles of the operation and modeling of this micro PKM is largely similar to a normal size Stewart Platform (SP). A modular design methodology is introduced for the construction of this micro PKM. Calibration results of this hybrid 3-UPU PKM are discussed in this paper.

Optimal Methodology for Synchronized Scheduling of Parallel Station Assembly with Air Transportation

We present an optimal methodology for synchronized scheduling of production assembly with air transportation to achieve accurate delivery with minimized cost in consumer electronics supply chain (CESC). This problem was motivated by a major PC manufacturer in consumer electronics industry, where it is required to schedule the delivery requirements to meet the customer needs in different parts of South East Asia. The overall problem is decomposed into two sub-problems which consist of an air transportation allocation problem and an assembly scheduling problem. The air transportation allocation problem is formulated as a Linear Programming Problem with earliness tardiness penalties for job orders. For the assembly scheduling problem, it is basically required to sequence the job orders on the assembly stations to minimize their waiting times before they are shipped by flights to their destinations. Hence the second sub-problem is modelled as a scheduling problem with earliness penalties. The earliness penalties are assumed to be independent of the job orders.

Proposal of a parallel architecture for a motion detection algorithm

This paper proposes a parallel architecture for estimation of the motion of an underwater robot. It is well known that image processing requires a huge amount of computation, mainly at low-level processing where the algorithms are dealing with a great number of data. In a motion estimation algorithm, correspondences between two images have to be solved at the low level. In the underwater imaging, normalised correlation can be a solution in the presence of non-uniform illumination. Due to its regular processing scheme, parallel implementation of the correspondence problem can be an adequate approach to reduce the computation time. Taking into consideration the complexity of the normalised correlation criteria, a new approach using parallel organisation of every processor from the architecture is proposed

Los acuerdos de protección y promoción recíproca de inversiones (APPRI) o biteral investment treaties (BIT) en Colombia

La inversión extranjera constituye una oportunidad de elevar los índices de crecimiento y desarrollo económico de Colombia. Desde la reforma económica de 1990-1994, el país cambió su política frente a temas como: la economía, las finanzas públicas, la estructura empresarial, el sector agrícola y la base tributaria, entre otros. En respuesta a este cambio, con la entrada de las políticas de corte neoliberal y el nuevo sistema político e institucional del país, se modificaron sus estructuras e instituciones. Asimismo surgieron nuevas prioridades. De ahí que se iniciaran también nuevas relaciones estratégicas‚ con otros Estados, para satisfacer estos nuevos intereses. Dentro de estas nuevas prioridades surgió el interés de atraer inversión extranjera directa y de portafolio. En ese momento‚ e inclusive ahora se hace necesario financiar la economía emergente y nada más propicio que la inversión extranjera para este propósito. Es decir, se complementa el crecimiento económico, con flujos de capital externo, que puede llegar en forma de inversión directa o de figuras financieras como las acciones, los bonos, etc.

Recurso informático aplicado al aula : proyecto BIT.

El proyecto se llevó a cabo en el CP Ramón Lanza de Cabezón de la Sal. Un gran número de profesores del centro se implicó asistiendo incluso a cursos de informática. Los objetivos de este proyecto están planteados por niveles educativos, siendo los generales los siguientes: 1. Aplicar programas educativos informáticos como refuerzo a otras áreas - lenguaje, matemáticas, conocimiento del medio, inglés, etc. 2. Desarrollar trabajos específicos de la zona occidental de Cantabria para hacer llegar al alumnado un mayor conocimiento del entorno donde habita. 3. Incorporar el ordenador como recurso importante en el proceso enseñanza-aprendizaje, para: motivar investigar, etc en las distintas etapas educativas. 4. Facilitar la adquisición y descubrimientos de destrezas y capacidades a través de interacciones con los demás. 5. Tratar aspectos transversales como complemento a las demás disciplinas. 6. Colaborar con la organización de centro, aplicando medios informáticos a su gestión: biblioteca, publicaciones, etc. 7. Participar en Talleres de Comunicación. 8. Posibilitar al alumnado el acceso a las nuevas tecnologías. En el desarrollo del proyecto se describen aquellas actividades que se llevaron a cabo como: Nociones básicas sobre el manejo de ordenadores: elementos que lo conforman. Creación de una mascota que está presente en el aula de informática. Desarrollo de los apuntes elaborados para la fase de iniciación: Mascota, Posición correcta, Normas generales del aula de informática, Mi PC, Unidad central, El teclado, El ratón, La impresora. Aplicación de programas como Paint o Pinto para afianzarse con la correcta utilización del ratón. Reconocimiento de letras y su impresión en pantalla en educación infantil. Exposición de programas multimedia en la idea de que el alumnado capte posibilidades de la informática. Los materiales utilizados fueron ordenadores, impresoras, material ofimático (disquettes, tinta), material de oficina.

The parallel diplomacy and the International Relations of the regions

The inclusion of subnational entities in international politics, breaks with the exclusive privilege of handling external relations by the States. Regions and municipalities have developed international policies that strengthen local affairs in cultural, economic, politic, security and strategic cooperation aspects, through the so-called parallel diplomacy activities. The influence of regional institutions in global affairs is growing; however paradiplomacy practice is not institutionalized and received little attention in international relation studies.

Modelling official and parallel exchange rates in Colombia under alternative regimes: a non-linear approach

We examine the long-run relationship between the parallel and the official exchange rate in Colombia over two regimes; a crawling peg period and a more flexible crawling band one. The short-run adjustment process of the parallel rate is examined both in a linear and a nonlinear context. We find that the change from the crawling peg to the crawling band regime did not affect the long-run relationship between the official and parallel exchange rates, but altered the short-run dynamics. Non-linear adjustment seems appropriate for the first period, mainly due to strict foreign controls that cause distortions in the transition back to equilibrium once disequilibrium occurs