Moderate exercise changes synaptic and cytoskeletal proteins in motor regions of the rat brain

Physical exercise is known to enhance brain function in several aspects. We evaluated the acute effects of a moderate forced exercise protocol on synaptic proteins, namely synapsin 1 (SYN) and synaptophysin (SYP), and structural proteins (neurofilaments, NFs) in rat brain regions related to motor function and often affected by neurodegenerative disorders. Immunohistochemistry, Western blotting and real-time PCR were used to analyze the expression of those proteins after 3, 7 and 15 days of exercise (EX3, EX7 and EX15). In the cerebellum, increase of SYN was observed at EX7 and EX15 and of NF68 at EX3. In the substantia nigra, increases of protein levels were observed for NF68 and NF160 at EX3. In the striatum, there was an increase of SYN at EX3 and EX7, of SYP at EX7 and of NF68 at EX3. In the cortex, decreased levels of NF68 and NF160 were observed at EX3, followed by an increase of NF68 at EX15. In the reticular formation, all NF proteins were increased at EX15. The mRNA data for each time-point and region also revealed significant exercise-related changes of SYN, SYP and NF expression. These results suggest that moderate physical exercise modulates synaptic and structural proteins in motor brain areas, which may play an important role in the exercise-dependent brain plasticity. (C) 2010 Elsevier B.V. All rights reserved.

Relative contribution of pre- and post-synaptic effects to the neostigmine-induced recovery of neuromuscular transmission blocked by vecuronium

The relative contribution of the pre- and post-synaptic effects to the neostigmine-induced recovery of neuromuscular transmission blocked by vecuronium was studied. A conjunction of myographical and electrophysiological techniques was employed. The preparation was the sciatic nerve-extensor digitorum longus muscle of the rat, in vitro. The physiological variables recorded were nerve-evoked twitches (generated at 0.1 Hz), tetanic contractions (generated at 50 Hz) and end-plate potentials (epps), generated in trains of 50 Hz. The epps were analyzed in: amplitude of first epp in the train; mean amplitude of the 30th to the 59th epp in the train (epps-plateau); half-decay time of the epp; early tetanic rundown of epps in the train; plateau tetanic rundown of epps in the train; quantal content of the epps and quantal size. In myographical experiments, a concentration of vecuronium was found (0.8 mu m) that affected both twitches and tetanic contractions and a concentration of neostigmine was found (0.048 mu m) that completely restored the twitch affected by vecuronium. The cellular effects of vecuronium and neostigmine, studied alone or in association, in the above-mentioned concentrations, were scrutinized by means of electrophysiological techniques. These showed that vecuronium alone decreased the peak amplitude, the quantal content of epps and the quantal size and reinforced the tetanic rundown of epps. Neostigmine alone increased the peak amplitude, the quantal content and the half-decay time of the epps. When employed in the presence of vecuronium, neostigmine increased both the quantal content of the epps (via a presynaptic effect) and the half-decay time of the epps (via a postsynaptic effect). Seeing the pre- and the post-synaptic effects of neostigmine were of similar magnitude, they permit to conclude that both these effects contributed significantly to the restoration by neostigmine of the neuromuscular transmission blocked by vecuronium.

Equivalent Circuits and Nanoplasmonics

We show how a circuit analysis, used widely in electrical engineering, finds application to problems of light wave injection and transport in subwavelength structures in the optical frequency range. Lumped circuit and transmission-line analysis may prove helpful in the design of plasmonic devices with standard, functional properties.

Claude Elwood Shannon e a symbolic analysis of relay and switching circuits: tornando o computador uma máquina semiótica.

O nome de Claude Elwood Shannon não é totalmente estranho aos pesquisadores de Comunicação Social. No entanto, parte de sua importância para a história da comunicação no século XX é pouco conhecida. Sua dissertação de mestrado e o artigo dela derivado (A Symbolic Analysis of Relay and Switching Circuits) foram essenciais para que o computador se tornasse uma máquina de comunicação e, conseqüentemente, penetrasse em nossa sociedade na forma como ocorre hoje. Este artigo revisa o primeiro grande trabalho de Shannon e explicita sua participação no contexto atual da comunicação.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Low cost BIST techniques for linear and non-linear analog circuits

With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.

Metamaterial inspired improved antennas and circuits

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Dinâmica da Plasticidade Sináptica em neurônios do hipocampo durante ciclos de sono: um estudo computacional

Several research lines show that sleep favors memory consolidation and learning. It has been proposed that the cognitive role of sleep is derived from a global scaling of synaptic weights, able to homeostatically restore the ability to learn new things, erasing memories overnight. This phenomenon is typical of slow-wave sleep (SWS) and characterized by non-Hebbian mechanisms, i.e., mechanisms independent of synchronous neuronal activity. Another view holds that sleep also triggers the specific enhancement of synaptic connections, carrying out the embossing of certain mnemonic traces within a lattice of synaptic weights rescaled each night. Such an embossing is understood as the combination of Hebbian and non-Hebbian mechanisms, capable of increasing and decreasing respectively the synaptic weights in complementary circuits, leading to selective memory improvement and a restructuring of synaptic configuration (SC) that can be crucial for the generation of new behaviors ( insights ). The empirical findings indicate that initiation of Hebbian plasticity during sleep occurs in the transition of the SWS to the stage of rapid eye movement (REM), possibly due to the significant differences between the firing rates regimes of the stages and the up-regulation of factors involved in longterm synaptic plasticity. In this study the theories of homeostasis and embossing were compared using an artificial neural network (ANN) fed with action potentials recorded in the hippocampus of rats during the sleep-wake cycle. In the simulation in which the ANN did not apply the long-term plasticity mechanisms during sleep (SWS-transition REM), the synaptic weights distribution was re-scaled inexorably, for its mean value proportional to the input firing rate, erasing the synaptic weights pattern that had been established initially. In contrast, when the long-term plasticity is modeled during the transition SWSREM, an increase of synaptic weights were observed in the range of initial/low values, redistributing effectively the weights in a way to reinforce a subset of synapses over time. The results suggest that a positive regulation coming from the long-term plasticity can completely change the role of sleep: its absence leads to forgetting; its presence leads to a positive mnemonic change