A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

A Monolithic Integrated Logic Circuit of Resonant Tunneling Diodes and a HEMT

A technology for the monolithic integration of resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs) is developed. Molecular beam epitaxy is used to grow an RTD on a HEMT structure on GaAs substrate. The RTD has a room temperature peak-to-valley ratio of 5.2:1 with a peak current density of 22.5kA/cm~2. The HEMT has a 1μm gate length with a-1V threshold voltage. A logic circuit called a monostableto-bistable transition logic element (MOBILE) circuit is developed. The experimental result confirms that the fabricated logic circuit operates successfully with frequency operations of up to 2GHz.

Millimeter-wave printed circuit board characterization using substrate integrated waveguide resonators

This paper proposes a substrate integrated waveguide
(SIW) cavity-based method that is compliant with
ground-signal–ground (GSG) probing technology for dielectric
characterization of printed circuit board materials at millimeter
wavelengths. This paper presents the theory necessary to retrieve
dielectric parameters from the resonant characteristics of SIW
cavities with particular attention placed on the coupling scheme
and means for obtaining the unloaded resonant frequency. Different
sets of samples are designed and measured to address the
influence of the manufacturing process on the method. Material
parameters are extracted at - and -band from measured data
with the effect of surface roughness of the circuit metallization
taken into account.

Testing symmetry and homogeneity in the almost ideal demand system with co-integrated data using fully modified estimation and the bootstrap

Conventional seemingly unrelated estimation of the almost ideal demand system is shown to lead to small sample bias and distortions in the size of a Wald test for symmetry and homogeneity when the data are co-integrated. A fully modified estimator is developed in an attempt to remedy these problems. It is shown that this estimator reduces the small sample bias but fails to eliminate the size distortion.. Bootstrapping is shown to be ineffective as a method of removing small sample bias in both the conventional and fully modified estimators. Bootstrapping is effective, however, as a method of removing. size distortion and performs equally well in this respect with both estimators.

The use of mechanisms and modes of toxic action in integrated testing strategies: the report and recommendations of a workshop held as part of the European Union OSIRIS Integrated Project

This report on The Potential of Mode of Action (MoA) Information Derived from Non-testing and Screening Methodologies to Support Informed Hazard Assessment, resulted from a workshop organised within OSIRIS (Optimised Strategies for Risk Assessment of Industrial Chemicals through Integration of Non-test and Test Information), a project partly funded by the EU Commission within the Sixth Framework Programme. The workshop was held in Liverpool, UK, on 30 October 2008, with 35 attendees. The goal of the OSIRIS project is to develop integrated testing strategies (ITS) fit for use in the REACH system, that would enable a significant increase in the use of non-testing information for regulatory decision making, and thus minimise the need for animal testing. One way to improve the evaluation of chemicals may be through categorisation by way of mechanisms or modes of toxic action. Defining such groups can enhance read-across possibilities and priority settings for certain toxic modes or chemical structures responsible for these toxic modes. Overall, this may result in a reduction of in vivo testing on organisms, through combining available data on mode of action and a focus on the potentially most-toxic groups. In this report, the possibilities of a mechanistic approach to assist in and guide ITS are explored, and the differences between human health and environmental areas are summarised.

Integrated testing strategy (ITS) for bioaccumulation assessment under REACH

REACH (registration, evaluation, authorisation and restriction of chemicals) regulation requires that all the chemicals produced or imported in Europe above 1 tonne/year are registered. To register a chemical, physicochemical, toxicological and ecotoxicological information needs to be reported in a dossier. REACH promotes the use of alternative methods to replace, refine and reduce the use of animal (eco)toxicity testing. Within the EU OSIRIS project, integrated testing strategies (ITSs) have been developed for the rational use of non-animal testing approaches in chemical hazard assessment. Here we present an ITS for evaluating the bioaccumulation potential of organic chemicals. The scheme includes the use of all available data (also the non-optimal ones), waiving schemes, analysis of physicochemical properties related to the end point and alternative methods (both in silico and in vitro). In vivo methods are used only as last resort. Using the ITS, in vivo testing could be waived for about 67% of the examined compounds, but bioaccumulation potential could be estimated on the basis of non-animal methods. The presented ITS is freely available through a web tool.

Optimizing the aquatic toxicity assessment under REACH through an integrated testing strategy (ITS).

To satisfy REACH requirements a high number of data on chemical of interest should be supplied to the European Chemicals Agency. To organize the various kinds of information and help the registrants to choose the best strategy to obtain the needed information limiting at the minimum the use of animal testing, integrated testing strategies (ITSs) schemes can be used. The present work deals with regulatory data requirements for assessing the hazards of chemicals to the aquatic pelagic environment. We present an ITS scheme for organizing and using the complex existing data available for aquatic toxicity assessment. An ITS to optimize the choice of the correct prediction strategy for aquatic pelagic toxicity is described. All existing information (like physico-chemical information), and all the alternative methods (like in silico, in vitro or the acute-to-chronic ratio) are considered. Moreover the weight of evidence approach to combine the available data is included.

Iowa improved driver licensing procedures demonstration project; closed circuit color television electro-mechanical teaching/testing licensing system. Final report.

National Highway Traffic Safety Administration, Washington, D.C.

Testing the expectations hypothesis when interest rates are near integrated /

Mode of access: Internet.

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Testing a gravity-based accessibility instrument to engage stakeholders into integrated LUT planning

The paper starts from the concern that while there is a large body of literature focusing on the theoretical definitions and measurements of accessibility, the extent to which such measures are used in planning practice is less clear. Previous reviews of accessibility instruments have in fact identified a gap between the clear theoretical assumptions and the infrequent applications of accessibility instruments in spatial and transport planning. In this paper we present the results of a structured-workshop involving private and public stakeholders to test usability of gravity-based accessibility measures (GraBaM) to assess integrated land-use and transport policies. The research is part of the COST Action TU1002 “Accessibility Instruments for Planning Practice” during which different accessibility instruments where tested for different case studies. Here we report on the empirical case study of Rome.

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.