Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

OpenMP task scheduling strategies to mitigate hardware variability in tightly-coupled shared memory clusters

In questa tesi sono stati apportati due importanti contributi nel campo degli acceleratori embedded many-core. Abbiamo implementato un runtime OpenMP ottimizzato per la gestione del tasking model per sistemi a processori strettamente accoppiati in cluster e poi interconnessi attraverso una network on chip. Ci siamo focalizzati sulla loro scalabilità e sul supporto di task di granularità fine, come è tipico nelle applicazioni embedded. Il secondo contributo di questa tesi è stata proporre una estensione del runtime di OpenMP che cerca di prevedere la manifestazione di errori dati da fenomeni di variability tramite una schedulazione efficiente del carico di lavoro.

Test hardware del secondo batch di schede ROD per il layer 2 del pixel detector dell'esperimento ATLAS al CERN

In questa tesi viene seguito il lavoro di test delle schede ROD del layer 2 del Pixel Detector dell’ esperimento ATLAS, che mira a verificare la loro corretta funzionalità, prima che vengano spedite nei laboratori del CERN. Queste nuove schede gestiscono i segnali in arrivo dal Pixel Detector di ATLAS, per poi inviarli ai computer per la successiva elaborazione. Le schede ROD andranno a sostituire le precedenti schede SiROD nella catena di acquisizione dati dell’esperimento, procedendo dal nuovo strato IBL, e proseguendo con i tre layer del Pixel Detector, corroborando l’aggiornamento tecnologico e prestazionale necessario in vista dell’incremento di luminosità dell’esperimento.

Realizzazione di un sistema di automazione domotica con tecnologia open-hardware

Il termine Domotica deriva dall’unione dei termini domus e robotics e spazia oltre alle competenze in ambito informatico ed elettronico, avvalendosi dell’architettura e di determinati campi dell’ingegneria come: energetica, edile, dell’ automazione, elettrotecnica, delle telecomunicazioni. La Domotica agevola gli aspetti della quotidianità all’interno dell’ambiente casalingo o, più in generale, di ambienti antropizzati. Questa tesi ha l’intento di spiegare come può essere realizzato un sistema domotizzato casalingo utilizzando dispositivi open-hardware. Inizialmente verranno messi in chiaro i concetti chiave generici di un sistema domotico e verranno discussi i prodotti attualmente in commercio e verrà fatta una piccola introduzione sul concetto di open-hardware. Successivamente verrà discusso il sistema realizzato dandone una panoramica, si esaminerà la strutturazione sia software che hardware e le tecnologie ed i dispositivi utilizzati, per poi enucleare casi d’uso. A seguire le conclusioni.

Hardware accelerated ray cast of volume data and volume gradient for an optimized splines-based multi-resolution 2D-3D registration

This paper describes a method for DRR generation as well as for volume gradients projection using hardware accelerated 2D texture mapping and accumulation buffering and demonstrates its application in 2D-3D registration of X-ray fluoroscopy to CT images. The robustness of the present registration scheme are guaranteed by taking advantage of a coarse-to-fine processing of the volume/image pyramids based on cubic B-splines. A human cadaveric spine specimen together with its ground truth was used to compare the present scheme with a purely software-based scheme in three aspects: accuracy, speed, and capture ranges. Our experiments revealed an equivalent accuracy and capture ranges but with much shorter registration time with the present scheme. More specifically, the results showed 0.8 mm average target registration error, 55 second average execution time per registration, and 10 mm and 10° capture ranges for the present scheme when tested on a 3.0 GHz Pentium 4 computer.

Potential for hardware-based techniques for reuse distance analysis

Reuse distance analysis, the prediction of how many distinct memory addresses will be accessed between two accesses to a given address, has been established as a useful technique in profile-based compiler optimization, but the cost of collecting the memory reuse profile has been prohibitive for some applications. In this report, we propose using the hardware monitoring facilities available in existing CPUs to gather an approximate reuse distance profile. The difficulties associated with this monitoring technique are discussed, most importantly that there is no obvious link between the reuse profile produced by hardware monitoring and the actual reuse behavior. Potential applications which would be made viable by a reliable hardware-based reuse distance analysis are identified.

Development of Hardware-In-the-Loop Simulation System for Hybrid Electric Vehicle Study

The development of embedded control systems for a Hybrid Electric Vehicle (HEV) is a challenging task due to the multidisciplinary nature of HEV powertrain and its complex structures. Hardware-In-the-Loop (HIL) simulation provides an open and convenient environment for the modeling, prototyping, testing and analyzing HEV control systems. This thesis focuses on the development of such a HIL system for the hybrid electric vehicle study. The hardware architecture of the HIL system, including dSPACE eDrive HIL simulator, MicroAutoBox II and MotoTron Engine Control Module (ECM), is introduced. Software used in the system includes dSPACE Real-Time Interface (RTI) blockset, Automotive Simulation Models (ASM), Matlab/Simulink/Stateflow, Real-time Workshop, ControlDesk Next Generation, ModelDesk and MotoHawk/MotoTune. A case study of the development of control systems for a single shaft parallel hybrid electric vehicle is presented to summarize the functionality of this HIL system.

Hierarchical Markov Random Fields Applied to Model Soft Tissue Deformations on Graphics Hardware

Many methodologies dealing with prediction or simulation of soft tissue deformations on medical image data require preprocessing of the data in order to produce a different shape representation that complies with standard methodologies, such as mass–spring networks, finite element method s (FEM). On the other hand, methodologies working directly on the image space normally do not take into account mechanical behavior of tissues and tend to lack physics foundations driving soft tissue deformations. This chapter presents a method to simulate soft tissue deformations based on coupled concepts from image analysis and mechanics theory. The proposed methodology is based on a robust stochastic approach that takes into account material properties retrieved directly from the image, concepts from continuum mechanics and FEM. The optimization framework is solved within a hierarchical Markov random field (HMRF) which is implemented on the graphics processor unit (GPU See Graphics processing unit ).

Rendering Falling Leaves on Graphics Hardware

There is a growing interest in simulating natural phenomena in computer graphics applications. Animating natural scenes in real time is one of the most challenging problems due to the inherent complexity of their structure, formed by millions of geometric entities, and the interactions that happen within. An example of natural scenario that is needed for games or simulation programs are forests. Forests are difficult to render because the huge amount of geometric entities and the large amount of detail to be represented. Moreover, the interactions between the objects (grass, leaves) and external forces such as wind are complex to model. In this paper we concentrate in the rendering of falling leaves at low cost. We present a technique that exploits graphics hardware in order to render thousands of leaves with different falling paths in real time and low memory requirements.

Plataforma de Integración Hardware-Software para Testbed de Redes de Sensores Inalámbricas

El campo de las redes de sensores inalámbricas ha cobrado gran importancia en esta última década ya que se han abierto diversas líneas de investigación con el fin de poder llevar a la práctica los conceptos y definiciones que envuelven el potencial de esta tecnología, y que está llamada a ser el futuro en la adquisición de datos de cualquier entorno físico de aplicación, mediante una herramienta basada en la autogestión y desatención durante largos periodos de tiempo, capacidad de tomar muestras cuando sea necesario a través de nodos sensores que se caractericen por el ahorro de energía y que puedan ser capaces de trabajar de forma autónoma durante meses, y que el carácter inalámbrico de la red a desplegar facilite las tareas de instalación y mantenimiento. Ello requiere que las condiciones para que una red de sensores inalámbrica sea la forma más viable de monitorizar un determinado entorno se base en ciertos requisitos de diseño, como lo es la baja tasa de transferencia de datos por parte de los nodos (estos deben ser capaces de transmitir la información recolectada desde los sensores y luego permanecer dormidos hasta una nueva adquisición), hardware enfocado al bajo consumo de energía con el fin de evitar cambios en la fuente de energía (baterías) durante largos periodos de tiempo, adaptabilidad al entorno de aplicación, flexibilidad y escalabilidad de la red si la aplicación hace necesario la inclusión de nuevos nodos o la modificación de los ya existentes, sin que ello suponga mayores dificultades en su desarrollo e implementación. El Centro de Electrónica industrial de la Universidad Politécnica de Madrid se incluye dentro de este último grupo, donde se ha diseñado una completa plataforma hardware para redes de sensores inalámbricas, con el fin de investigar las potencialidades, dificultades y retos que supone el realizar un despliegue de nodos inalámbricos en cumplimiento de características primordiales como autonomía, flexibilidad y escalabilidad de la red, además de la autogestión de los dispositivos que forman parte de ella. El presente trabajo de investigación se centra en cubrir estas necesidades, por lo que su principal objetivo es la creación de una plataforma de integración hardware-software que permita explotar todas las potencialidades de la arquitectura Cookies a través de una herramienta que facilite el despliegue, control y mantenimiento de una red de sensores inalámbrica, con el fin último de contar con un sistema total para el prototipado rápido de aplicaciones, soporte de pruebas de nuevos desarrollos y la posibilidad de implementación de dicha plataforma en cualquier entorno real, siendo sólo necesario realizar pequeños ajustes desde el más alto nivel de abstracción para que el sistema sea capaz de adaptarse por sí solo. Para cumplir tales propósitos y lograr una completa integración del sistema conjunto, ha sido necesario fijar principalmente tres líneas de trabajo que se enmarcan dentro de los objetivos específicos del presente proyecto, las cuales se detallan a continuación: Bibliotecas Software modulares: Basada en la filosofía de modularidad y flexibilidad de la plataforma hardware, se hace imprescindible primeramente contar con una plataforma software para el control de todos y cada uno de los elementos que componen al nodo Cookie, a partir de bloques funcionales que permitan gestionar desde el núcleo de procesamiento principal todas las características de la plataforma. Esto permitirá asegurar el control de los recursos hardware y facilitar la utilización de la plataforma desde un nivel más alto de abstracción, sólo con la configuración de parámetros estandarizados para el funcionamiento de la misma. Perfil de aplicación Cookies: Después de contar con bloques software que permitan controlar las características de bajo nivel del nodo inalámbrico, es necesario crear una herramienta para la estandarización de la forma en la que se comunican los dispositivos a nivel de aplicación, con el fin de gestionar las características y atributos de los nodos sensores de forma remota y facilitar el entendimiento entre ellos. Para ello, es necesario fijar ciertas directivas y reglas que permitan homogeneizar la gestión de tareas asociadas a los nodos Cookies, a través del diseño de un perfil de aplicación. Testbed para redes de sensores: Como resultado de las dos líneas anteriores de trabajo, la idea es contar con un instrumento que permita realizar pruebas reales haciendo uso de la plataforma de integración HW-SW, a partir de la gestión de todas las características y potencialidades que ofrece el perfil de aplicación creado y así facilitar el desarrollo de prototipos para aplicaciones basadas en redes de sensores inalámbricas, de forma rápida y eficiente. En este sentido, la idea es contar con un banco de pruebas basado en un despliegue de nodos Cookies que pueda ser controlado desde un ordenador central a través de una interfaz de usuario, desde el cual se lleva a cabo la monitorización y actuación sobre la red inalámbrica. Con el fin de lograr todos los objetivos planteados, ha sido necesario realizar un exhaustivo estudio de la plataforma hardware descrita anteriormente con el fin de conocer la forma en la que interactúan cada uno de los elementos incluidos en los nodos, así como la arquitectura y filosofía de los mismos, para poder llevar a cabo la integración con el software y, como se verá más adelante, realizar ajustes en el hardware para poder implementar correctamente las funcionalidades diseñadas. Por otro lado, ha sido necesario analizar las características de la especificación ZigBee y, sobre todo, las propiedades que posee el módulo de comunicaciones que incluye la plataforma hardware, el ETRX2, con el fin de poder realizar una configuración y gestión adecuada de los nodos a través de la red inalámbrica, aprovechando las posibilidades y recursos que ofrece dicho módulo.

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems

This paper presents an analysis of the fault tolerance achieved by an autonomous, fully embedded evolvable hardware system, which uses a combination of partial dynamic reconfiguration and an evolutionary algorithm (EA). It demonstrates that the system may self-recover from both transient and cumulative permanent faults. This self-adaptive system, based on a 2D array of 16 (4×4) Processing Elements (PEs), is tested with an image filtering application. Results show that it may properly recover from faults in up to 3 PEs, that is, more than 18% cumulative permanent faults. Two fault models are used for testing purposes, at PE and CLB levels. Two self-healing strategies are also introduced, depending on whether fault diagnosis is available or not. They are based on scrubbing, fitness evaluation, dynamic partial reconfiguration and in-system evolutionary adaptation. Since most of these adaptability features are already available on the system for its normal operation, resource cost for self-healing is very low (only some code additions in the internal microprocessor core)

Inner-Hair Cells Parameterized-Hardware Implementation for Personalized Auditory Nerve Stimulation

In this paper the hardware implementation of an inner hair cell model is presented. Main features of the design are the use of Meddis’ transduction structure and the methodology for Design with Reusability. Which allows future migration to new hardware and design refinements for speech processing and custom-made hearing aids