Photosensitization of different Candida species by low power laser light

The aim of this study was to evaluate the effects of the laser radiation (685 nm) associated with photosensitizers on viability of different species of Candida genus. Suspensions of Candida albicans, Candida dubliniensis, Candida krusei and Candida tropicalis, containing 106 viable cells per milliliter were obtained with the aid of a Neubauer's chamber. From each species, 10 samples of the cell suspension were irradiated with diode laser (685 nm) with 28 J/cm(2) in the presence of methylene blue (0.1 mg/ml), 10 samples were only treated with methylene blue, 10 samples were irradiated with laser in the absence of the dye, 10 samples were treated with the dye and irradiated with laser light and 10 samples were exposed to neither the laser light nor to the methylene blue dye. From each sample, serial dilutions of 10(-2) and 10(-3) were obtained and aliquots of 0.1 ml of each dilution were plated in duplicate on Sabouraud dextrose agar. After incubation at 37 degrees C for 48 h, the number of colony-forming units (CFU/ml) was obtained and data were submitted to ANOVA and Tukey's test (p < 0.05). Laser radiation in the presence of methylene blue reduced the number of CFU/ml in 88.6% for C. albicans, 84.8% for C. dubliniensis, 91.6% for C krusei and 82.3% for C tropicalis. Despite of this, only laser radiation or methylene blue did not reduce significantly the number of CFU/ml of Candida samples, except for C tropicalis. It could be concluded that the photo activation of methylene blue by the red laser radiation at 685 nm presented fungicide effect on all Candida species studied. (c) 2006 Elsevier B.V. All rights reserved.

On designing linearly-tunable ultra-low voltage CMOS gm-C filters

A linearly-tunable ULV transconductor featuring excellent stability of the processed signal common-mode voltage upon tuning, critical for very-low voltage applications, is presented. Its employment to the synthesis of CMOS gm-C high-frequency and voiceband filters is discussed. SPICE data describe the filter characteristics. For a 1.3 V-supply, their nominal passband frequencies are 1.0 MHz and 3.78 KHz, respectively, with tuning rates of 12.52 KHz/mV and 0.16 KHz/m V, input-referred noise spectral density of 1.3 μV/Hz1/2 and 5.0μV/Hz1/2 and standby consumption of 0.87 mW and 11.8 μW. Large-signal distortion given by THD = 1% corresponds to a differential output-swing of 360 mVpp and 480 mVpp, respectively. Common-mode voltage deviation is less than 4 mV over tuning interval.

Histological study of hamster buccal mucosa following topical application of DMBA and exposition to low power 337 nm laser light

The aim of the present work is to analyze the histological changes on hamster buccal mucosa caused by the topical use of 7,12-dimethylbenzanthracene (DMBA) and exposition to a 220 μJ/pulse nitrogen laser light (@ 337 nm) at an average power of 2,3 mW. Twenty-one hamsters divided into two experimental groups were treated six times with DMBA. One hamster was kept as control. Group I was composed by ten hamsters and was submitted only to DMBA. Group II, also with ten hamsters, received the same treatment as group I and was exposed to the laser radiation. The time duration of each irradiation section was 10 seconds. All the treatment happened in alternated days. The histological analysis took place twice, after the end of the treatment and after sixty days. Both experimental groups presented dilatation of vessels, thickening of the epithelial tissue and the presence of inflammatory infiltrates. The preliminary results indicates that in group II the number of dilated vessels and its new area are much more significant than in group I.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

A novel programmable PFC based hybrid rectifier for ultra clean power application

A novel hybrid high power rectifier capable to achieve unity power factor is proposed in this paper. Single-phase SEPIC rectifiers are associated in parallel with each leg of three-phase 6-pulse diode rectifier resulting in a programmable input current waveform structure. In this paper it is described the principles of operation of the proposed converter with detailed simulation and experimental results. For a total harmonic distortion of the input line current (THDI) less than 2% the rated power of the SEPIC rectifiers is 33%. Therefore, power rating of the SEPIC parallel converters is a fraction of the output power, on the range of 20% to 33% of the nominal output power, making the proposed solution economically viable for high power installations, with fast pay back of the investment. Moreover, retrofits to existing installations are also possible with this proposed topology, since the parallel path can be easily controlled by integration with the already existing de-link. Experimental results are presented for a 3 kW implemented prototype, in order to verify the developed analysis.

Permanent Magnet Hall Thruster for satellite orbit raising with low power energy consumption

Electric propulsion is now a succeful method for primary propulsion of deep space long duration missions and for geosyncronous satellite attitude control. Closed Drift Thruster, so called Hall Thruster or SPT (Stationary Plasma Thruster), was primarily conceived in USSR (the ancient Soviet Union) and, since then, it has been developed by space agencies, space research institutes and industries in several countries such as France, USA, Israel, Russian Federation and Brazil. In this work we present the main features of the Permanent Magnet Hall Thruster (PMHT) developed at the Plasma Laboratory of the University of Brasilia. The idea of using an array of permanent magnets, instead of an electromagnet, to produce a radial magnetic field inside the plasma channel of the thruster is very significant. It allows the development of a Hall Thruster with power consumption low enough to be used in small and medium size satellites. Description of a new vacuum chamber used to test the second prototype of the PMHT (PHALL II) will be given. PHALL II has an aluminum plasma chamber and is smaller with 15 cm diameter and will contain rare earth magnets. We will show plasma density and temperature space profiles inside and outside the thruster channel. Ion temperature measurements based on Doppler broadening of spectral lines and ion energy measurements are also shown. Based on the measured plasma parameters we constructed an aptitude figure of the PMHT. It contains the specific impulse, total thrust, propellant flow rate and power consumption necessary for orbit raising of satellites. Based on previous studies of geosyncronous satellite orbit positioning we perform numerical simulations of satellite orbit raising from an altitude of 700 km to 36000 km using a PMHT operating in the 100 mN - 500 mN thrust range. In order to perform these calculations integration techniques were used. The main simulation paraters were orbit raising time, fuel mass, total satellite mass, thrust and exaust velocity. We conclude comparing our results with results obtainned with known space missions performed with Hall Thrusters. © 2008 by the American Institute of Aeronautics and Astronautics, Inc.

Single stage converters for low power stand-alone and grid-connected PV systems

This work presents the evaluation of different power electronic integrated converters suitable for photovoltaic applications, in order to reduce complexity and improve reliability. The rated voltages available in Photovoltaic (PV) modules have usually low values for applications such as regulated output voltages in stand-alone or grid-connected configurations. In these cases, a boost stage or a transformer will be necessary. Transformers have low efficiencies, heavy weights and have been used only when galvanic isolation is mandatory. Furthermore, high-frequency transformers increase the converter complexity. Therefore, the most usual topologies use a boost stage and one inverter stage cascaded. However, the complexity, size, weight, cost and lifetime might be improved considering the integration of both stages. In this context, some integrated converters are analyzed and compared in this paper in order to support future evaluations and trends for low power single-phase inverters for PV systems. Power decoupling, MPPT and Tri-State modulations are also considered. Finally, simulation and experimental results are presented and compared for the analyzed topologies. © 2011 IEEE.

Evaluation of integrated inverter topologies for low power PV systems

This work presents the stage integration in power electronics converters as a suitable solution for solar photovoltaic inverters. The rated voltages available in Photovoltaic (PV) modules have usually low values for applications such as regulated output voltages in stand-alone or grid-connected configurations. In these cases, a boost stage or a transformer will be necessary. Transformers have low efficiencies, heavy weights and have been used only when galvanic isolation is mandatory. Furthermore, high-frequency transformers increase the converter complexity. Therefore, the most usual topologies use a boost stage and one inverter stage cascaded. However, the complexity, size, weight, cost and lifetime might be improved considering the integration of both stages. These are the expected features to turn attractive this kind of integrated structures. Therefore, some integrated converters are analyzed and compared in this paper in order to support future evaluations and trends for low power single-phase inverters for PV systems. © 2011 IEEE.

A single-phase single-stage buck-boost inverter intended for low power alternative energy conversion systems: Analysis, design and experimentation

This paper presents the operational analysis of the single-phase integrated buck-boost inverter. This topology is able to convert the DC input voltage into AC voltage with a high static gain, low harmonic content and acceptable efficiency, all in one single-stage. Main functionality aspects are explained, design procedure, system modeling and control, and also component requirements are detailed. Main simulation results are included, and two prototypes were implemented and experimentally tested, where its results are compared with those corresponding to similar topologies available in literature. © 2012 IEEE.

Effects of time exposure and low power sonochemical treatment on ZnO mesostructures

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A low-power silicon-on-insulator PWM discriminator for biomedical applications

A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a double-integration concept and does not require dc filtering. Nonoverlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mu m single-metal SOI fabrication process and has an effective area of 2mm(2) Typically, the measured resolution of encoding parameter a was better than 10% at 6MHz and V-DD=3.3V. Stand-by consumption is around 340 mu W. Pulses with frequencies up to 15MHz and alpha = 10% can be discriminated for V-DD spanning from 2.3V to 3.3V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Ultra-low friction coefficient in alumina-silicon nitride pair lubricated with water

In a ball-on-disc wear test, an alumina ceramic body sliding against a silicon nitride ceramic body in water achieved an ultra-low friction coefficient (ULFC) of 0.004. The profilometer and EDX measurements indicated that the ULFC regime in this unmated Al2O3-Si3N4 pair was achieved because of the formation of a flat and smooth interface of nanometric roughness, which favored the hydrodynamic lubrication. The triboreactions formed silicon and aluminum hydroxides which contributed to decrease roughness and shear stress at the contact interface. This behavior enables the development of low energy loss water-based tribological systems using oxide ceramics. 13 2012 Elsevier B.V. All rights reserved.

Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS

Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.