Design and analysis of an all-optical processor for modular arithmetic

We present a logical design of an all-optical processor that performs modular arithmetic. The overall design is based a set of interconnected modules that use all-optical gates to perform simple logical functions. The all-optical logic gates are based on the semiconductor optical amplifier nonlinear loop. Simulation results are presented and some practical design issues are discussed.

Design of fast core node processor for packet forwarding without header modification in optical networks

We present a design of a fast all-optical core-node processor that performs packet-forwarding in optical networks without header-modification. The design is based on bit-serial architecture using TOADs as logic-gates that perform modulo-arithmetic to forward packets.

Networks of Evolutionary Processors: Java Implementation of a Threaded Processor

This paper is focused on a parallel JAVA implementation of a processor defined in a Network of Evolutionary Processors. Processor description is based on JDom, which provides a complete, Java-based solution for accessing, manipulating, and outputting XML data from Java code. Communication among different processor to obtain a fully functional simulation of a Network of Evolutionary Processors will be treated in future. A safe-thread model of processors performs all parallel operations such as rules and filters. A non-deterministic behavior of processors is achieved with a thread for each rule and for each filter (input and output). Different results of a processor evolution are shown.

Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.

ARM processor modeling at a cycle accurate level in systemC

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

ARM processor modeling at a cycle accurate level in systemC

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Exploiting Nested Parallelism on Heterogeneous Processors

Heterogeneous computing systems have become common in modern processor architectures. These systems, such as those released by AMD, Intel, and Nvidia, include both CPU and GPU cores on a single die available with reduced communication overhead compared to their discrete predecessors. Currently, discrete CPU/GPU systems are limited, requiring larger, regular, highly-parallel workloads to overcome the communication costs of the system. Without the traditional communication delay assumed between GPUs and CPUs, we believe non-traditional workloads could be targeted for GPU execution. Specifically, this thesis focuses on the execution model of nested parallel workloads on heterogeneous systems. We have designed a simulation flow which utilizes widely used CPU and GPU simulators to model heterogeneous computing architectures. We then applied this simulator to non-traditional GPU workloads using different execution models. We also have proposed a new execution model for nested parallelism allowing users to exploit these heterogeneous systems to reduce execution time.

Implementation of soft processor based SOC for JPEG compression on FPGA

With the advent of semiconductor process and EDA tools technology, IC designers can integrate more functions. However, to reduce the demand of time-to-market and tackle the increasing complexity of SoC, the need of fast prototyping and testing is growing. Taking advantage of deep submicron technology, modern FPGAs provide a fast and low-cost prototyping with large logic resources and high performance. So the hardware is mapped onto an emulation platform based on FPGA that mimics the behaviour of SOC. In this paper we use FPGA as a system on chip which is then used for image compression by 2-D DCT respectively and proposed SoC for image compression using soft core Microblaze. The JPEG standard defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. Proposed SoC for JPEG compression has been implemented on FPGA Spartan-6 SP605 evaluation board using Xilinx platform studio, because field programmable gate array have reconfigurable hardware architecture. Hence the JPEG image with high speed and reduced size can be obtained at low risk and low power consumption of about 0.699W. The proposed SoC for image compression is evaluated at 83.33MHz on Xilinx Spartan-6 FPGA.

DEVELOPMENT OF ION EXCHANGE MODELS FOR WATER TREATMENT AND APPLICATION TO THE INTERNATIONAL SPACE STATION WATER PROCESSOR

The International Space Station (ISS) requires a substantial amount of potable water for use by the crew. The economic and logistic limitations of transporting the vast amount of water required onboard the ISS necessitate onboard recovery and reuse of the aqueous waste streams. Various treatment technologies are employed within the ISS water processor to render the waste water potable, including filtration, ion exchange, adsorption, and catalytic wet oxidation. The ion exchange resins and adsorption media are combined in multifiltration beds for removal of ionic and organic compounds. A mathematical model (MFBMODEL™) designed to predict the performance of a multifiltration (MF) bed was developed. MFBMODEL consists of ion exchange models for describing the behavior of the different resin types in a MF bed (e.g., mixed bed, strong acid cation, strong base anion, and weak base anion exchange resins) and an adsorption model capable of predicting the performance of the adsorbents in a MF bed. Multicomponent ion exchange ii equilibrium models that incorporate the water formation reaction, electroneutrality condition, and degree of ionization of weak acids and bases for mixed bed, strong acid cation, strong base anion, and weak base anion exchange resins were developed and verified. The equilibrium models developed use a tanks-inseries approach that allows for consideration of variable influent concentrations. The adsorption modeling approach was developed in related studies and application within the MFBMODEL framework was demonstrated in the Appendix to this study. MFBMODEL consists of a graphical user interface programmed in Visual Basic and Fortran computational routines. This dissertation shows MF bed modeling results in which the model is verified for a surrogate of the ISS waste shower and handwash stream. In addition, a multicomponent ion exchange model that incorporates mass transfer effects was developed, which is capable of describing the performance of strong acid cation (SAC) and strong base anion (SBA) exchange resins, but not including reaction effects. This dissertation presents results showing the mass transfer model's capability to predict the performance of binary and multicomponent column data for SAC and SBA exchange resins. The ion exchange equilibrium and mass transfer models developed in this study are also applicable to terrestrial water treatment systems. They could be applied for removal of cations and anions from groundwater (e.g., hardness, nitrate, perchlorate) and from industrial process waters (e.g. boiler water, ultrapure water in the semiconductor industry).

A digital signal processor controlled smart battery charger for photovoltaic power systems

An off-grid photovoltaic power system requires an energy storage system, especially batteries, for mitigation of variability and intermittency problems, and for assured service reliability and availability. The longevity and reliability of such batteries depend on the effectiveness of the charging system. This paper presents the modelling, simulation and hardware implementation of a four-stage switch-mode charger based on the single-ended primary inductance converter. The digital signal processor based controller implements algorithms for the system's power balance control, maximum power point tracking to improve charging speed and efficiency, four-stage optimal charging, and system's protection. The protection algorithm provides over-charge, overdischarge, over-temperature and short circuit protection capabilities. The proposed system has the following advantages: ability to continuously charge the batteries even at reduced solar irradiation, higher efficiency, and use of adaptive thermally compensated set points for optimum performance. A prototype is built and experimental results are presented to validate the simulation results.

LeadLine: intel for savvy South Carolina port clients - April 2014

The South Carolina Port LeadLine is a monthly marketing brief of the South Carolina Ports Authority.

LeadLine: intel for savvy South Carolina port clients - February 2014

The South Carolina Port LeadLine is a monthly marketing brief of the South Carolina Ports Authority.

LeadLine: intel for savvy South Carolina port clients - December 2014

The South Carolina Port LeadLine is a monthly marketing brief of the South Carolina Ports Authority.

LeadLine: intel for savvy South Carolina port clients - February 2015

The South Carolina Port LeadLine is a monthly marketing brief of the South Carolina Ports Authority.