All-optical regenerative memory using a single device

In recent years the optical domain has been traditionally reserved for node-to-node transmission with the processing and switching achieved entirely in the electrical domain. However, with the constantly increasing demand for bandwidth and the resultant increase in transmission speeds, there is a very real fear that current electronic technology as used for processing will not be able to cope with future demands. Fuelled by this requirement for faster processing speeds, considerable research is currently being carried out into the potential of All-optical processing. One of the fundamental obstacles in realising All-optical processing is the requirement for All-optical buffering. Without all-optical buffers it is extremely difficult to resolve situations such as contention and congestion. Many devices have been proposed to solve this problem however none of them provide the perfect solution. The subject of this research is to experimentally demonstrate a novel all-optical memory device. Unlike many previously demonstrated optical storage devices the device under consideration utilises only a single loop mirror and a single SOA as its switch, whilst providing full regenerative capabilities required for long-term storage. I will explain some of the principles and characteristics of the device, which will then be experimentally demonstrated. The device configuration will then be studied and investigated as to its suitability for Hybrid Integrated Technology.

Suggestion from the Past?

Mathematics Subject Classification: 26A33 (main), 35A22, 78A25, 93A30

Nanophotonics of optical fibers

This review is concerned with nanoscale effects in highly transparent dielectric photonic structures fabricated from optical fibers. In contrast to those in plasmonics, these structures do not contain metal particles, wires, or films with nanoscale dimensions. Nevertheless, a nanoscale perturbation of the fiber radius can significantly alter their performance. This paper consists of three parts. The first part considers propagation of light in thin optical fibers (microfibers) having the radius of the order of 100 nanometers to 1 micron. The fundamental mode propagating along a microfiber has an evanescent field which may be strongly expanded into the external area. Then, the cross-sectional dimensions of the mode and transmission losses are very sensitive to small variations of the microfiber radius. Under certain conditions, a change of just a few nanometers in the microfiber radius can significantly affect its transmission characteristics and, in particular, lead to the transition from the waveguiding to non-waveguiding regime. The second part of the review considers slow propagation of whispering gallery modes in fibers having the radius of the order of 10–100 microns. The propagation of these modes along the fiber axis is so slow that they can be governed by extremely small nanoscale changes of the optical fiber radius. This phenomenon is exploited in SNAP (surface nanoscale axial photonics), a new platform for fabrication of miniature super-low-loss photonic integrated circuits with unprecedented sub-angstrom precision. The SNAP theory and applications are overviewed. The third part of this review describes methods of characterization of the radius variation of microfibers and regular optical fibers with sub-nanometer precision.

Uniquely Identifiable Tamper-Evident Device Using Coupling between Subwavelength Gratings

Reliability and sensitive information protection are critical aspects of integrated circuits. A novel technique using near-field evanescent wave coupling from two subwavelength gratings (SWGs), with the input laser source delivered through an optical fiber is presented for tamper evidence of electronic components. The first grating of the pair of coupled subwavelength gratings (CSWGs) was milled directly on the output facet of the silica fiber using focused ion beam (FIB) etching. The second grating was patterned using e-beam lithography and etched into a glass substrate using reactive ion etching (RIE). The slightest intrusion attempt would separate the CSWGs and eliminate near-field coupling between the gratings. Tampering, therefore, would become evident. Computer simulations guided the design for optimal operation of the security solution. The physical dimensions of the SWGs, i.e. period and thickness, were optimized, for a 650 nm illuminating wavelength. The optimal dimensions resulted in a 560 nm grating period for the first grating etched in the silica optical fiber and 420 nm for the second grating etched in borosilicate glass. The incident light beam had a half-width at half-maximum (HWHM) of at least 7 µm to allow discernible higher transmission orders, and a HWHM of 28 µm for minimum noise. The minimum number of individual grating lines present on the optical fiber facet was identified as 15 lines. Grating rotation due to the cylindrical geometry of the fiber resulted in a rotation of the far-field pattern, corresponding to the rotation angle of moiré fringes. With the goal of later adding authentication to tamper evidence, the concept of CSWGs signature was also modeled by introducing random and planned variations in the glass grating. The fiber was placed on a stage supported by a nanomanipulator, which permitted three-dimensional displacement while maintaining the fiber tip normal to the surface of the glass substrate. A 650 nm diode laser was fixed to a translation mount that transmitted the light source through the optical fiber, and the output intensity was measured using a silicon photodiode. The evanescent wave coupling output results for the CSWGs were measured and compared to the simulation results.

Broadband RF current detector

The problems to be solved in this thesis were 1) development of a broadband RF preamplifier to be used with non-ferrous current probes so that the amplified signal exceeds the errors due to cable pickup, no detection is needed in this application, and 2) development of a self-contained device that amplifies and detects the output from a nonferrous current probe, providing a digital readout of the current. These instruments have been completed and are being tested for use by the National Institutes of Occupational Safety and Health (NIOSH). The self-contained current meter operates at frequencies up to 600 MHz, and detects currents as low as 8 mA . At these current magnitudes, the probe (pick-up coil) will output a voltage of 500μV (-53 dBm on 50Ω) which will have to be raised above 0 dBm. The final circuit uses a RF mixer as a variable attenuator in order to increase the dynamic range, two Monolithic Microwave Integrated Circuits (MMIC) for preamplification, a final broadband amplifier to raise the output compression point, a Schottky diode detector, a sample and hold circuit, and a liquid crystal digital panel meter.

Design and analysis of micro-channel heat-exchanger embedded in Low Temperature Co-fire Ceramic (LTCC)

Increased device density, switching speeds of integrated circuits and decrease in package size is placing new demands for high power thermal-management. The convectional method of forced air cooling with passive heat sink can handle heat fluxes up-to 3-5W/cm2; however current microprocessors are operating at levels of 100W/cm2, This demands the usage of novel thermal-management systems. In this work, water-cooling systems with active heat sink are embedded in the substrate. The research involved fabricating LTCC substrates of various configurations - an open-duct substrate, the second with thermal vias and the third with thermal vias and free-standing metal columns and metal foil. Thermal testing was performed experimentally and these results are compared with CFD results. An overall thermal resistance for the base substrate is demonstrated to be 3.4oC/W-cm2. Addition of thermal vias reduces the effective resistance of the system by 7times and further addition of free standing columns reduced it by 20times.

Implementação de uma matriz de neurônios dinamicamente reconfigurável para descrição de topologias de redes neurais artificiais multilayer perceptrons

The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.

Implementação de uma matriz de neurônios dinamicamente reconfigurável para descrição de topologias de redes neurais artificiais multilayer perceptrons

The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.

Micromachined silicon lenses for terahertz applications

Silicon microlenses are a very important tool for coupling terahertz (THz) radiation into antennas and detectors in integrated circuits. They can be used in a large array structures at this frequency range reducing considerably the crosstalk between the pixels. Drops of photoresist have been deposited and their shape transferred into the silicon by means of a Reactive Ion Etching (RIE) process. Large silicon lenses with a few mm diameter (between 1.5 and 4.5 mm) and hundreds of μm height (between 50 and 350 μm) have been fabricated. The surface of such lenses has been characterized using Scanning Electron Microscopy (SEM) and Atomic Force Microscopy (AFM), resulting in a surface roughness of about ∼3 μm, good enough for any THz application. The beam profile at the focal plane of such lenses has been measured at a wavelength of 10.6 μm using a tomographic knife-edge technique and a CO2 laser.

Design, Fabrication, and Characterization of Carbon Nanotube Field Emission Devices for Advanced Applications

Carbon nanotubes (CNTs) have recently emerged as promising candidates for electron field emission (FE) cathodes in integrated FE devices. These nanostructured carbon materials possess exceptional properties and their synthesis can be thoroughly controlled. Their integration into advanced electronic devices, including not only FE cathodes, but sensors, energy storage devices, and circuit components, has seen rapid growth in recent years. The results of the studies presented here demonstrate that the CNT field emitter is an excellent candidate for next generation vacuum microelectronics and related electron emission devices in several advanced applications.

The work presented in this study addresses determining factors that currently confine the performance and application of CNT-FE devices. Characterization studies and improvements to the FE properties of CNTs, along with Micro-Electro-Mechanical Systems (MEMS) design and fabrication, were utilized in achieving these goals. Important performance limiting parameters, including emitter lifetime and failure from poor substrate adhesion, are examined. The compatibility and integration of CNT emitters with the governing MEMS substrate (i.e., polycrystalline silicon), and its impact on these performance limiting parameters, are reported. CNT growth mechanisms and kinetics were investigated and compared to silicon (100) to improve the design of CNT emitter integrated MEMS based electronic devices, specifically in vacuum microelectronic device (VMD) applications.

Improved growth allowed for design and development of novel cold-cathode FE devices utilizing CNT field emitters. A chemical ionization (CI) source based on a CNT-FE electron source was developed and evaluated in a commercial desktop mass spectrometer for explosives trace detection. This work demonstrated the first reported use of a CNT-based ion source capable of collecting CI mass spectra. The CNT-FE source demonstrated low power requirements, pulsing capabilities, and average lifetimes of over 320 hours when operated in constant emission mode under elevated pressures, without sacrificing performance. Additionally, a novel packaged ion source for miniature mass spectrometer applications using CNT emitters, a MEMS based Nier-type geometry, and a Low Temperature Cofired Ceramic (LTCC) 3D scaffold with integrated ion optics were developed and characterized. While previous research has shown other devices capable of collecting ion currents on chip, this LTCC packaged MEMS micro-ion source demonstrated improvements in energy and angular dispersion as well as the ability to direct the ions out of the packaged source and towards a mass analyzer. Simulations and experimental design, fabrication, and characterization were used to make these improvements.

Finally, novel CNT-FE devices were developed to investigate their potential to perform as active circuit elements in VMD circuits. Difficulty integrating devices at micron-scales has hindered the use of vacuum electronic devices in integrated circuits, despite the unique advantages they offer in select applications. Using a combination of particle trajectory simulation and experimental characterization, device performance in an integrated platform was investigated. Solutions to the difficulties in operating multiple devices in close proximity and enhancing electron transmission (i.e., reducing grid loss) are explored in detail. A systematic and iterative process was used to develop isolation structures that reduced crosstalk between neighboring devices from 15% on average, to nearly zero. Innovative geometries and a new operational mode reduced grid loss by nearly threefold, thereby improving transmission of the emitted cathode current to the anode from 25% in initial designs to 70% on average. These performance enhancements are important enablers for larger scale integration and for the realization of complex vacuum microelectronic circuits.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Microwave Plasma Assisted ALD Development for the Deposition of Gate Oxides & ALD of High-k Dielectrics

The semiconductor industry's urge towards faster, smaller and cheaper integrated circuits has lead the industry to smaller node devices. The integrated circuits that are now under volume production belong to 22 nm and 14 nm technology nodes. In 2007 the 45 nm technology came with the revolutionary high- /metal gate structure. 22 nm technology utilizes fully depleted tri-gate transistor structure. The 14 nm technology is a continuation of the 22 nm technology. Intel is using second generation tri-gate technology in 14 nm devices. After 14 nm, the semiconductor industry is expected to continue the scaling with 10 nm devices followed by 7 nm. Recently, IBM has announced successful production of 7 nm node test chips. This is the fashion how nanoelectronics industry is proceeding with its scaling trend. For the present node of technologies selective deposition and selective removal of the materials are required. Atomic layer deposition and the atomic layer etching are the respective techniques used for selective deposition and selective removal. Atomic layer deposition still remains as a futuristic manufacturing approach that deposits materials and lms in exact places. In addition to the nano/microelectronics industry, ALD is also widening its application areas and acceptance. The usage of ALD equipments in industry exhibits a diversi cation trend. With this trend, large area, batch processing, particle ALD and plasma enhanced like ALD equipments are becoming prominent in industrial applications. In this work, the development of an atomic layer deposition tool with microwave plasma capability is described, which is a ordable even for lightly funded research labs.