Proposta de um sistema de monitoramento do processo de retificação plana baseado em plataforma de hardware livre e sensor de baixo custo

O processo de retificação é considerado um dos últimos na cadeia de produção de peças de precisão. Assim, é essencial ter um sistema de monitoramento confiável para este processo. Neste trabalho é proposto um sistema de medição de vibração, rápido e versátil, baseado na plataforma de prototipagem eletrônica de hardware livre Arduino, com objetivo de monitorar em tempo real o processo de retificação plana, especialmente no que diz respeito à condição da peça retificada. Para este trabalho ensaios experimentais foram realizados numa máquina retificadora plana, empregando um rebolo de óxido de alumínio e uma peça de aço ABNT 1020. Por meio de um sensor piezelétrico de PZT (Pb-Lead Zirconate Titanate) de baixo custo, instalado junto à peça e conectado a uma das portas analógicas do hardware, foi possível medir o sinal de vibração durante o processo de retificação. Verificou-se que, a medida com que o rebolo perdia sua capacidade de corte, em função das consecutivas passadas sobre a peça, ocorria também uma significativa diminuição dos valores médios do sinal de vibração. Tal diminuição do sinal de vibração pode indicar o momento que o rebolo deve ser dressado, permitindo monitorar a qualidade superficial da peça durante o processo de retificação, evitando danos como é o caso da queima superficial. O princípio de operação e as principais características dessa técnica foram investigados, bem como algumas de suas limitações práticas.

Analysis of simple hardware efficiency for temperature measurement in agriculture and environment

This work focuses basically on the design and analysis of simple and low cost hardware systems efficiency for temperature measurement in agricultural area. The main objective is to prove quantitatively, through statistical data analysis, to what extent a simple hardware designed with inexpensive components can be used safely in the indoor temperature measurement in farm buildings, such as greenhouses, warehouse or silos. To verify the of simple hardware efficiency, its data were compared with data from measurements with a high performance LabVIEW platform. This work proved that a simple hardware based on a microcontroller and the LM35 sensor can perform well. It presented a good accuracy but a relatively low precision that can be improved when performed some consecutive signal sampling and then used its average value. Although there are many papers that explain these components, this work has the distinction of presenting a data analysis in numerical form and using high performance systems to ensure critical data comparison.

Rock Hill Hardware Company Records - Accession 220

The Rock Hill Hardware Company was organized on June 4, 1893 by A.R. Smith and John Gelzer, A.A. Barron and his sons R.E. and W.L. bought Smith out in 1896 and by 1907 had acquired the whole firm. The Barron family owned and operated it until it closed in 1978. The collection consists of a 1906 ledger, financial records, a photograph, a seed license, World War II ration booklets, and newspaper clippings.

Actualización, consolidación, migración y contingencia de un entorno hardware y software para la gestión de bases de datos

[ES]El objetivo de este Trabajo es el de actualizar un entorno de gestión de bases de datos existente a la versión 11.2 del software de bases de datos Oracle y a una plataforma hardware de última generación. Se migran con tiempo de parada cero varias bases de datos dispersas en distintos servidores a un entorno consolidado de dos nodos dispuestos en alta disponibilidad tipo "activo-activo" mediante Oracle RAC y respaldado por un entorno de contingencia totalmente independiente y sincronizado en tiempo real mediante Oracle GoldenGate. Se realiza un estudio del entorno actual y, realizando una estimación de crecimiento, se propone una configuración de hardware y software mínima para implementar con garantías de éxito los requerimientos del entorno de gestión de bases de datos a corto y medio plazo. Una vez adquirido el hardware, se lleva a cabo la instalación, actualización y configuración del Sistema Operativo y el acceso redundado de los servidores a la cabina de almacenamiento. Posteriormente se instala el software de clúster de Oracle, el software de la base de datos y se crea una instancia que albergará los esquemas requeridos de las bases de datos a consolidar. Seguidamente se migran los esquemas al entorno consolidado y se establece la replicación de éstos en tiempo real con la máquina de contingencia usando en ambos casos Oracle GoldenGate. Finalmente se crea y prueba un esquema de copias de seguridad que incluye copias lógicas y físicas de la propia base de datos y de archivos de configuración del clúster a partir de los cuales será posible restaurar el entorno completamente.

Project-based learning using robots with open-source hardware and software

[EN]One of the main issues of the current education system is the lack of student motivation. This aspect together with the permanent change that the Information and Communications Technologies involve represents a major challenge for the teacher: to continuously update contents and to keep awake the student’s interest. A tremendously useful tool in classrooms consists on the integration of projects with participative and collaborative dynamics, where the teacher acts mainly as a guidance to the student activity instead of being a mere knowledge and evaluation transmitter. As a specific example of project based learning, the EDUROVs project consists on building an economic underwater robot using low cost materials, but allowing the integration and programming of many accessories and sensors with minimum budget using opensource hardware and software.

Hardware and software development of a multichannel readout board named CARLOSrx for the ALICE experiment

ALICE, that is an experiment held at CERN using the LHC, is specialized in analyzing lead-ion collisions. ALICE will study the properties of quarkgluon plasma, a state of matter where quarks and gluons, under conditions of very high temperatures and densities, are no longer confined inside hadrons. Such a state of matter probably existed just after the Big Bang, before particles such as protons and neutrons were formed. The SDD detector, one of the ALICE subdetectors, is part of the ITS that is composed by 6 cylindrical layers with the innermost one attached to the beam pipe. The ITS tracks and identifies particles near the interaction point, it also aligns the tracks of the articles detected by more external detectors. The two ITS middle layers contain the whole 260 SDD detectors. A multichannel readout board, called CARLOSrx, receives at the same time the data coming from 12 SDD detectors. In total there are 24 CARLOSrx boards needed to read data coming from all the SDD modules (detector plus front end electronics). CARLOSrx packs data coming from the front end electronics through optical link connections, it stores them in a large data FIFO and then it sends them to the DAQ system. Each CARLOSrx is composed by two boards. One is called CARLOSrx data, that reads data coming from the SDD detectors and configures the FEE; the other one is called CARLOSrx clock, that sends the clock signal to all the FEE. This thesis contains a description of the hardware design and firmware features of both CARLOSrx data and CARLOSrx clock boards, which deal with all the SDD readout chain. A description of the software tools necessary to test and configure the front end electronics will be presented at the end of the thesis.

Sviluppo di modelli motore e veicolo per l'analisi di strategie di controllo in applicazioni Software e Hardware In the Loop

This work describes the development of a simulation tool which allows the simulation of the Internal Combustion Engine (ICE), the transmission and the vehicle dynamics. It is a control oriented simulation tool, designed in order to perform both off-line (Software In the Loop) and on-line (Hardware In the Loop) simulation. In the first case the simulation tool can be used in order to optimize Engine Control Unit strategies (as far as regard, for example, the fuel consumption or the performance of the engine), while in the second case it can be used in order to test the control system. In recent years the use of HIL simulations has proved to be very useful in developing and testing of control systems. Hardware In the Loop simulation is a technology where the actual vehicles, engines or other components are replaced by a real time simulation, based on a mathematical model and running in a real time processor. The processor reads ECU (Engine Control Unit) output signals which would normally feed the actuators and, by using mathematical models, provides the signals which would be produced by the actual sensors. The simulation tool, fully designed within Simulink, includes the possibility to simulate the only engine, the transmission and vehicle dynamics and the engine along with the vehicle and transmission dynamics, allowing in this case to evaluate the performance and the operating conditions of the Internal Combustion Engine, once it is installed on a given vehicle. Furthermore the simulation tool includes different level of complexity, since it is possible to use, for example, either a zero-dimensional or a one-dimensional model of the intake system (in this case only for off-line application, because of the higher computational effort). Given these preliminary remarks, an important goal of this work is the development of a simulation environment that can be easily adapted to different engine types (single- or multi-cylinder, four-stroke or two-stroke, diesel or gasoline) and transmission architecture without reprogramming. Also, the same simulation tool can be rapidly configured both for off-line and real-time application. The Matlab-Simulink environment has been adopted to achieve such objectives, since its graphical programming interface allows building flexible and reconfigurable models, and real-time simulation is possible with standard, off-the-shelf software and hardware platforms (such as dSPACE systems).

Multi Processor Systems On Chip with Configurable Hardware Acceleration

The evolution of the electronics embedded applications forces electronics systems designers to match their ever increasing requirements. This evolution pushes the computational power of digital signal processing systems, as well as the energy required to accomplish the computations, due to the increasing mobility of such applications. Current approaches used to match these requirements relies on the adoption of application specific signal processors. Such kind of devices exploits powerful accelerators, which are able to match both performance and energy requirements. On the other hand, the too high specificity of such accelerators often results in a lack of flexibility which affects non-recurrent engineering costs, time to market, and market volumes too. The state of the art mainly proposes two solutions to overcome these issues with the ambition of delivering reasonable performance and energy efficiency: reconfigurable computing and multi-processors computing. All of these solutions benefits from the post-fabrication programmability, that definitively results in an increased flexibility. Nevertheless, the gap between these approaches and dedicated hardware is still too high for many application domains, especially when targeting the mobile world. In this scenario, flexible and energy efficient acceleration can be achieved by merging these two computational paradigms, in order to address all the above introduced constraints. This thesis focuses on the exploration of the design and application spectrum of reconfigurable computing, exploited as application specific accelerators for multi-processors systems on chip. More specifically, it introduces a reconfigurable digital signal processor featuring a heterogeneous set of reconfigurable engines, and a homogeneous multi-core system, exploiting three different flavours of reconfigurable and mask-programmable technologies as implementation platform for applications specific accelerators. In this work, the various trade-offs concerning the utilization multi-core platforms and the different configuration technologies are explored, characterizing the design space of the proposed approach in terms of programmability, performance, energy efficiency and manufacturing costs.

Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems

The new generation of multicore processors opens new perspectives for the design of embedded systems. Multiprocessing, however, poses new challenges to the scheduling of real-time applications, in which the ever-increasing computational demands are constantly flanked by the need of meeting critical time constraints. Many research works have contributed to this field introducing new advanced scheduling algorithms. However, despite many of these works have solidly demonstrated their effectiveness, the actual support for multiprocessor real-time scheduling offered by current operating systems is still very limited. This dissertation deals with implementative aspects of real-time schedulers in modern embedded multiprocessor systems. The first contribution is represented by an open-source scheduling framework, which is capable of realizing complex multiprocessor scheduling policies, such as G-EDF, on conventional operating systems exploiting only their native scheduler from user-space. A set of experimental evaluations compare the proposed solution to other research projects that pursue the same goals by means of kernel modifications, highlighting comparable scheduling performances. The principles that underpin the operation of the framework, originally designed for symmetric multiprocessors, have been further extended first to asymmetric ones, which are subjected to major restrictions such as the lack of support for task migrations, and later to re-programmable hardware architectures (FPGAs). In the latter case, this work introduces a scheduling accelerator, which offloads most of the scheduling operations to the hardware and exhibits extremely low scheduling jitter. The realization of a portable scheduling framework presented many interesting software challenges. One of these has been represented by timekeeping. In this regard, a further contribution is represented by a novel data structure, called addressable binary heap (ABH). Such ABH, which is conceptually a pointer-based implementation of a binary heap, shows very interesting average and worst-case performances when addressing the problem of tick-less timekeeping of high-resolution timers.

Advances in hardware and molecular design of polarizing agents for dynamic nuclear polarization

Die Kernmagnetresonanz (NMR) ist eine vielseitige Technik, die auf spin-tragende Kerne angewiesen ist. Seit ihrer Entdeckung ist die Kernmagnetresonanz zu einem unverzichtbaren Werkzeug in unzähligen Anwendungen der Physik, Chemie, Biologie und Medizin geworden. Das größte Problem der NMR ist ihre geringe Sensitivtät auf Grund der sehr kleinen Energieaufspaltung bei Raumtemperatur. Für Protonenspins, die das größte magnetogyrische Verhältnis besitzen, ist der Polarisationsgrad selbst in den größten verfügbaren Magnetfeldern (24 T) nur ~7*10^(-5).rnDurch die geringe inhärente Polarisation ist folglich eine theoretische Sensitivitätssteigerung von mehr als 10^4 möglich. rnIn dieser Arbeit wurden verschiedene technische Aspekte und unterschiedliche Polarisationsagenzien für Dynamic Nuclear Polarization (DNP) untersucht.rnDie technische Entwicklung des mobilen Aufbaus umfasst die Verwendung eines neuen Halbach Magneten, die Konstruktion neuer Probenköpfe und den automatisierten Ablauf der Experimente mittels eines LabVIEW basierten Programms. Desweiteren wurden zwei neue Polarisationsagenzien mit besonderen Merkmalen für den Overhauser und den Tieftemperatur DNP getestet. Zusätzlich konnte die Durchführbarkeit von NMR Experimenten an Heterokernen (19F und 13C) im mobilen Aufbau bei 0,35 T gezeigt werden. Diese Ergebnisse zeigen die Möglichkeiten der Polarisationstechnik DNP auf, wenn Heterokerne mit einem kleinen magnetogyrischen Verhältnis polarisiert werden müssen.rnDie Sensitivitätssteigerung sollte viele neue Anwendungen, speziell in der Medizin, ermöglichen.

Test hardware del primo batch di schede rod per l'esperimento atlas ibl.

L’acceleratore di particelle LHC, al CERN di Ginevra, permette studi molto rilevanti nell'ambito della fisica subnucleare. L’importanza che ricopre in questo campo il rivelatore è grandissima ed è per questo che si utilizzano tecnologie d’avanguardia nella sua costruzione. É altresì fondamentale disporre di un sistema di acquisizione dati quanto più moderno ma sopratutto efficiente. Tale sistema infatti è necessario per gestire tutti i segnali elettrici che derivano dalla conversione dell’evento fisico, passaggio necessario per rendere misurabili e quantificabili le grandezze di interesse. In particolare in questa tesi viene seguito il lavoro di test delle schede ROD dell’esperimento ATLAS IBL, che mira a verificare la loro corretta funzionalità, prima che vengano spedite nei laboratori del CERN. Queste nuove schede gestiscono i segnali in arrivo dal Pixel Detector di ATLAS, per poi inviarli ai computer per la successiva elaborazione. Un sistema simile era già implementato e funzionante, ma il degrado dei chip ha causato una perdita di prestazioni, che ha reso necessario l’inserimento di un layer aggiuntivo. Il nuovo strato di rivelatori a pixel, denominato Insertable Barrel Layer (IBL), porta così un aggiornamento tecnologico e prestazionale all'interno del Pixel Detector di ATLAS, andando a ristabilire l’efficacia del sistema.

Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.