Effect of fault resistance and grid short circuit MVA on impedance seen by distance relays on lines fed from wind turbine generating units (WTGU)

This paper deals with line protection challenges experienced in system having substantial wind generation penetration. Two types of WTGU: Doubly Fed (DFIG) and Squirrel Cage (SCIG) Induction Generators are simulated and connected to grid with single circuit transmission line. The paper summarizes analytical investigations carried out on the impedance seen by distance relays by varying fault resistances and grid short circuit MVA, for the protection of such transmission lines during faults. The results are also compared with systems having conventional synchronous machine connected to the grid.

Reactive power and voltage control in grid connected wind farms

Wind power, as an alternative to fossil fuels, is plentiful, renewable, widely distributed, clean, produces no greenhouse gas emissions during operation, and uses little land. In operation, the overall cost per unit of energy produced is similar to the cost for new coal and natural gas installations. However, the stochastic behaviour of wind speeds leads to significant disharmony between wind energy production and electricity demand. Wind generation suffers from an intermittent characteristics due to the own diurnal and seasonal patterns of the wind behaviour. Both reactive power and voltage control are important under varying operating conditions of wind farm. To optimize reactive power flow and to keep voltages in limit, an optimization method is proposed in this paper. The objective proposed is minimization of the voltage deviations of the load buses (Vdesired). The approach considers the reactive power limits of wind generators and co-ordinates the transformer taps. This algorithm has been tested under practically varying conditions simulated on a test system. The results are obtained on a system of 50-bus real life equivalent power network. The result shows the efficiency of the proposed method.

Mitigation of lower order harmonics in a grid-connected single-phase PV inverter

In this paper, a simple single-phase grid-connected photovoltaic (PV) inverter topology consisting of a boost section, a low-voltage single-phase inverter with an inductive filter, and a step-up transformer interfacing the grid is considered. Ideally, this topology will not inject any lower order harmonics into the grid due to high-frequency pulse width modulation operation. However, the nonideal factors in the system such as core saturation-induced distorted magnetizing current of the transformer and the dead time of the inverter, etc., contribute to a significant amount of lower order harmonics in the grid current. A novel design of inverter current control that mitigates lower order harmonics is presented in this paper. An adaptive harmonic compensation technique and its design are proposed for the lower order harmonic compensation. In addition, a proportional-resonant-integral (PRI) controller and its design are also proposed. This controller eliminates the dc component in the control system, which introduces even harmonics in the grid current in the topology considered. The dynamics of the system due to the interaction between the PRI controller and the adaptive compensation scheme is also analyzed. The complete design has been validated with experimental results and good agreement with theoretical analysis of the overall system is observed.

A multi-winding transformer based power converter topology for a growing DC Micro-grid structure

A DC micro-grid essentially consists of power ports, bidirectional power converter and a controller structure that enables the control of dynamic power flow. In this paper, a prototype of a micro-grid structure using a recently proposed multi-winding transformer based power converter has been implemented. The power converter topology is further extended to multiple transformer cores in order to form a growing micro-grid structure. Additionally, modifications have been made in order to incorporate a battery charge controller with the main power circuit. All the other advantages of the power converter and its control scheme are still preserved.

Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Ferromagnetic Resonance Study on a Grid of Permalloy Nanowires

We report ferromagnetic resonance (FMR) study on a grid formed with permalloy nanowires to understand the spin wave dynamics. The presence of two sets of magnetic nanowires perpendicular to each other in the same device enables better control over spin waves. The grid was fabricated using e-beam lithography followed by DC-Magnetron sputtering and liftoff technique. It has dimensions of 800 +/- 10 and 400 +/- 10 nm as periods along X and Y directions with permalloy wires of width 145 +/- 10 nm. FMR studies were done at X-band (9.4 GHz) with the field sweep up to 1 Tesla. The in-plane angular variation of resonant fields shows that there are two well separated modes present, indicating two uniaxial anisotropy axes which are perpendicular to each other. The variation in the intensities in the FMR signal w.r.t. the grid angle is used to describe the spin wave confinement in different regions of the grid. We also explained the asymmetry in the magnetic properties caused by the geometrical property of the rectangular grid and the origin for the peak splitting for the modes occurring at higher resonant fields. Micromagnetic simulations based on OOMMF with two dimensional periodic boundary conditions (2D-PBC) are used to support our experimental findings.

Block Sparse Estimator for Grid Matching in Single Snapshot DoA Estimation

In this work, the grid mismatch problem for a single snapshot direction of arrival estimation problem is studied. We derive a Bayesian Cramer-Rao bound for the grid mismatch problem with the errors in variables model and propose a block sparse estimator for grid matching and sparse recovery.

Analysis and design of split-capacitor resistive-inductive passive damping for LCL filters in grid-connected inverters

Grid-connected inverters require a third-order LCL filter to meet standards such as the IEEE Std. 519-1992 while being compact and cost-effective. LCL filter introduces resonance, which needs to be damped through active or passive methods. Passive damping schemes have less control complexity and are more reliable. This study explores the split-capacitor resistive-inductive (SC-RL) passive damping scheme. The SC-RL damped LCL filter is modelled using state space approach. Using this model, the power loss and damping are analysed. Based on the analysis, the SC-RL scheme is shown to have lower losses than other simpler passive damping methods. This makes the SC-RL scheme suitable for high power applications. A method for component selection that minimises the power loss in the damping resistors while keeping the system well damped is proposed. The design selection takes into account the influence of switching frequency, resonance frequency and the choice of inductance and capacitance values of the filter on the damping component selection. The use of normalised parameters makes it suitable for a wide range of design applications. Analytical results show the losses and quality factor to be in the range of 0.05-0.1% and 2.0-2.5, respectively, which are validated experimentally.

Delay optimal scheduling of a discrete-time batch service queue for point-to-point channel code rate selection

We consider the problem of characterizing the minimum average delay, or equivalently the minimum average queue length, of message symbols randomly arriving to the transmitter queue of a point-to-point link which dynamically selects a (n, k) block code from a given collection. The system is modeled by a discrete time queue with an IID batch arrival process and batch service. We obtain a lower bound on the minimum average queue length, which is the optimal value for a linear program, using only the mean (λ) and variance (σ2) of the batch arrivals. For a finite collection of (n, k) codes the minimum achievable average queue length is shown to be Θ(1/ε) as ε ↓ 0 where ε is the difference between the maximum code rate and λ. We obtain a sufficient condition for code rate selection policies to achieve this optimal growth rate. A simple family of policies that use only one block code each as well as two other heuristic policies are shown to be weakly optimal in the sense of achieving the 1/ε growth rate. An appropriate selection from the family of policies that use only one block code each is also shown to achieve the optimal coefficient σ2/2 of the 1/ε growth rate. We compare the performance of the heuristic policies with the minimum achievable average queue length and the lower bound numerically. For a countable collection of (n, k) codes, the optimal average queue length is shown to be Ω(1/ε). We illustrate the selectivity among policies of the growth rate optimality criterion for both finite and countable collections of (n, k) block codes.

Harmonic Current Injection based Powerline Communication Method for Grid Connected Single Phase Inverters in Domestic Microgrids

The following paper presents a Powerline Communication (PLC) Method for Single Phase interfaced inverters in domestic microgrids. The PLC method is based on the injection of a repeating sequence of a specific harmonic, which is then modulated on the fundamental component of the grid current supplied by the inverters to the microgrid. The power flow and information exchange are simultaneously accomplished by the grid interacting inverters based on current programmed vector control, hence there is no need for dedicated hardware. Simulation results have been shown for inter-inverter communication under different operating conditions to propose the viability. These simulations have been experimentally validated and the corresponding results have also been presented in the paper.

Using Relationships for Matching Textual Domain Models with Existing Code

We address the task of mapping a given textual domain model (e.g., an industry-standard reference model) for a given domain (e.g., ERP), with the source code of an independently developed application in the same domain. This has applications in improving the understandability of an existing application, migrating it to a more flexible architecture, or integrating it with other related applications. We use the vector-space model to abstractly represent domain model elements as well as source-code artifacts. The key novelty in our approach is to leverage the relationships between source-code artifacts in a principled way to improve the mapping process. We describe experiments wherein we apply our approach to the task of matching two real, open-source applications to corresponding industry-standard domain models. We demonstrate the overall usefulness of our approach, as well as the role of our propagation techniques in improving the precision and recall of the mapping task.

Generating Efficient Data Movement Code for Heterogeneous Architectures with Distributed-Memory

Programming for parallel architectures that do not have a shared address space is extremely difficult due to the need for explicit communication between memories of different compute devices. A heterogeneous system with CPUs and multiple GPUs, or a distributed-memory cluster are examples of such systems. Past works that try to automate data movement for distributed-memory architectures can lead to excessive redundant communication. In this paper, we propose an automatic data movement scheme that minimizes the volume of communication between compute devices in heterogeneous and distributed-memory systems. We show that by partitioning data dependences in a particular non-trivial way, one can generate data movement code that results in the minimum volume for a vast majority of cases. The techniques are applicable to any sequence of affine loop nests and works on top of any choice of loop transformations, parallelization, and computation placement. The data movement code generated minimizes the volume of communication for a particular configuration of these. We use a combination of powerful static analyses relying on the polyhedral compiler framework and lightweight runtime routines they generate, to build a source-to-source transformation tool that automatically generates communication code. We demonstrate that the tool is scalable and leads to substantial gains in efficiency. On a heterogeneous system, the communication volume is reduced by a factor of 11X to 83X over state-of-the-art, translating into a mean execution time speedup of 1.53X. On a distributed-memory cluster, our scheme reduces the communication volume by a factor of 1.4X to 63.5X over state-of-the-art, resulting in a mean speedup of 1.55X. In addition, our scheme yields a mean speedup of 2.19X over hand-optimized UPC codes.

Coordination of Reactive Power in Grid-Connected Wind Farms for Voltage Stability Enhancement

This paper studies the feasibility of utilizing the reactive power of grid-connected variable-speed wind generators to enhance the steady-state voltage stability margin of the system. Allowing wind generators to work at maximum reactive power limit may cause the system to operate near the steady-state stability limit, which is undesirable. This necessitates proper coordination of reactive power output of wind generators with other reactive power controllers in the grid. This paper presents a trust region framework for coordinating reactive output of wind generators-with other reactive sources for voltage stability enhancement. Case studies on 418-bus equivalent system of Indian southern grid indicates the effectiveness of proposed methodology in enhancing the steady-state voltage stability margin.

A Grid Simulator to Evaluate Control Performance of Grid-Connected Inverters

Grid simulators are used to test the control performance of grid-connected inverters under a wide range of grid disturbance conditions. In the present work, a three phase back-to-back connected inverter sharing a common dc bus has been programmed as a grid simulator. Three phase balanced disturbance voltages applied to three-phase balanced loads has been considered in the present work. The developed grid simulator can generate three phase balanced voltage sags, voltage swells, frequency deviations and phase jumps. The grid simulator uses a novel disturbance generation algorithm. The algorithm allows the user to reference the disturbance to any of the three phases at any desired phase angle. Further, the exit of the disturbance condition can be referenced to the desired phase angle of any phase by adjusting the duration of the disturbance. The grid simulator hardware has been tested with different loads – a linear purely resistive load, a non-linear diode-bridge load and a grid-connected inverter load.

LDPC Code Designs Based on root I Matrices

LDPC codes can be constructed by tiling permutation matrices that belong to the square root of identity type and similar algebraic structures. We investigate into the properties of such codes. We also present code structures that are amenable for efficient encoding.