Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

Design of a compact polarization beam splitter based on a deformed photonic crystal directional coupler

In this paper a compact polarization beam splitter based on a deformed photonic crystal directional coupler is designed and simulated. The transverse-electric (TE) guided mode and transverse-magnetic (TM) guided mode are split due to different guiding mechanisms. The effect of the shape deformation of the air holes on the coupler is studied. It discovered that the coupling strength of the coupled waveguides is strongly enhanced by introducing elliptical airholes, which reduce the device length to less than 18.5 mu m. A finite-difference time-domain simulation is performed to evaluate the performance of the device, and the extinction ratios for both TE and TM polarized light are higher than 20 dB.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

Compact four-channel reconfigurable optical add-drop multiplexer using silicon photonic wire

We designed and fabricated a four-channel reconfigurable optical add-drop multiplexer based on silicon photonic wire waveguide, which is controlled through the thermo-optic effect. The effective footprint of the device is about 1000 x 500 mu m(2). The minimum insertion loss including the transmission loss and coupling loss is about 10.7 dB. The tuning bandwidth is about 17 nm, the average tuning efficiency about 6.11 mW/nm and the tuning speed about 24.5 kHz. (c) 2009 Elsevier B.V. All rights reserved.

The compact microcrystalline Si thin film with structure uniformity in the growth direction by hydrogen dilution profile

The hydrogen dilution profiling (HDP) technique has been developed to improve the quality and the crystalline uniformity in the growth direction of mu c-Si:H thin films prepared by hot-wire chemical-vapor deposition. The high H dilution in the initial growth stage reduces the amorphous transition layer from 30-50 to less than 10 nm. The uniformity of crystalline content X-c in the growth direction was much improved by the proper design of hydrogen dilution profiling which effectively controls the nonuniform transition region of Xc from 300 to less than 30 nm. Furthermore, the HDP approach restrains the formation of microvoids in mu c-Si: H thin films with a high Xc and enhances the compactness of the film. As a result the stability of mu c-Si: H thin films by HDP against the oxygen diffusion, as well as the electrical property, is much improved. (c) 2005 American Institute of Physics.

Design and fabrication of compact nonblocking 4X4 optical matrix switch on silicon-on-insulator by anisotropic chemical etching

A folding nonblocking 4 X 4 optical matrix switch in simplified-tree architecture was designed and fabricated on a silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were connected by total internal reflection mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide (KOH) anisotropic chemical etching of silicon was employed. The device has a compact size of 20 X 3.2 mm(2) and a fast response of 8 +/- 1 mu s. Power consumption of 2 x 2 SE and excess loss per mirror were 145 mW and -1.1 dB, respectively. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Geometrical learning, descriptive geometry, and biomimetic pattern recognition

Studies on learning problems from geometry perspective have attracted an ever increasing attention in machine learning, leaded by achievements on information geometry. This paper proposes a different geometrical learning from the perspective of high-dimensional descriptive geometry. Geometrical properties of high-dimensional structures underlying a set of samples are learned via successive projections from the higher dimension to the lower dimension until two-dimensional Euclidean plane, under guidance of the established properties and theorems in high-dimensional descriptive geometry. Specifically, we introduce a hyper sausage like geometry shape for learning samples and provides a geometrical learning algorithm for specifying the hyper sausage shapes, which is then applied to biomimetic pattern recognition. Experimental results are presented to show that the proposed approach outperforms three types of support vector machines with either a three degree polynomial kernel or a radial basis function kernel, especially in the cases of high-dimensional samples of a finite size. (c) 2005 Elsevier B.V. All rights reserved.

Resonant cavity based compact efficient antireflection structures for photonic crystals

We propose an effective admittance ( EA) method to design antireflection structures for two-dimensional photonic crystals (PCs). We demonstrate that a compact and efficient antireflection structure, which is difficult to obtain by the conventional admittance matching method, can be readily designed by the EA method. The antireflection structure consists of an air slot resonant cavity that is constructed only with the materials that constitute the PC. Compared with a bare PC, the reflection from a PC with an antireflection structure is reduced by two orders of magnitude over a wide bandwidth. To confirm the presented EA method, finite-difference time-domain (FDTD) simulations are performed, and the results from the FDTD and the EA method are in good agreement.

Compact SOI arrayed waveguide grating demultiplexer with broad spectral response

A compact eight-channel flat spectral response arrayed waveguide grating (AWG) multiplexer based on siliconon-insulator (SOI) materials has been fabricated on the planar lightwave circuit (PLC). The 1-dB bandwidth of 48 GHz and 3-dB bandwidth of 69 GHz are obtained for the 100 GHz channel spacing. Not only non-adjacent crosstalk but also adjacent crosstalk are less than -25 dB. The on-chip propagation loss range is from 3.5 to 3.9 dB, and the 2 total device size is 1.5 x 1.0 cm(2). (c) 2005 Elsevier B.V. All rights reserved.

Compact 3-dB tapered multimode interference coupler in silicon-on-insulator

We have fabricated a compact 3-dB multimode interference coupler with a large silicon-on-insulator cross section. To reduce the length of the usual symmetric interference multimode interference coupler, we propose using a parabolically tapered structure. The length of the device is 398 mum. The device has a uniformity of 0.28 dB. (C) 2001 Optical Society of America.

Ultra-compact silicon-on-insulator optical filter based on sidewall Bragg grating

Micro-cavity structure composed of silicon wire with 240nm square cross section and two symmetrical sidewall waveguide Bragg gratings is fabricated and studied for the operation under telecommunication wavelengths. Optical filter of quasi-TE mode was realized based on this cavity. In such micro-cavity, optical quality factor (Q) was measured up to 380 with a 4.8nm free spectral range (FSR) and 12dB fringe contrast (FC). The measured group index of silicon waveguide with only 240nm square cross section was between 3.80 and 5.43. It is the first time group delay of silicon wire waveguide with such small core dimension is studied. Larger group delay can be expected after optimizing the design parameters and the fabrication process.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

Theoretical and Experimental Studies of an Ultra-compact Photonic Crystal Corner Mirror Based on Silicon-On-Insulator

An ultra-compact silicon-on-insulator based photonic crystal corner mirror is designed and optimized. A sample is then successfully fabricated with extra losses 1.1 +/- 0.4dB for transverse-electronic (M) polarization for wavelength range of 1510-1630nm.