999 resultados para Blackboard Architecture


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Architects regularly employ design as a problem-solving tool in the built environment. Within the design process, architects apply design thinking to reframe problems as opportunities, take advantage of contradictory information to develop new solutions, and differentiate outcomes based on context. This research aims to investigate how design can be better positioned to develop greater differentiated value to an architect’s current service offering, and how design as a strategy could be applied as a driver of business innovation within the Australian architecture industry. The research will explore literature relating to the future of architecture, the application of design thinking, and the benefits of strategic design. The future intent of the research is to develop strategies that improve the value offering of architects, and develop design led solutions that could be applied successfully to the business of architecture.

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Simultaneous consideration of both performance and reliability issues is important in the choice of computer architectures for real-time aerospace applications. One of the requirements for such a fault-tolerant computer system is the characteristic of graceful degradation. A shared and replicated resources computing system represents such an architecture. In this paper, a combinatorial model is used for the evaluation of the instruction execution rate of a degradable, replicated resources computing system such as a modular multiprocessor system. Next, a method is presented to evaluate the computation reliability of such a system utilizing a reliability graph model and the instruction execution rate. Finally, this computation reliability measure, which simultaneously describes both performance and reliability, is applied as a constraint in an architecture optimization model for such computing systems. Index Terms-Architecture optimization, computation

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The influence of the architecture of the Byzantine capital spread to the Mediterranean provinces with travelling masters and architects. In this study the architecture of the Constantinopolitan School has been detected on the basis of the typology of churches, completed by certain morphological aspects when necessary. The impact of the Constantinopolitan workshops appears to have been more important than previously realized. This research revealed that the Constantinopolitan composite domed inscribed-cross type or cross-in-square spread everywhere to the Balkans and it was assumed soon by the local schools of architecture. In addition, two novel variants were invented on the basis of this model: the semi-composite type and the so-called Athonite type. In the latter variant lateral conches, choroi, were added for liturgical reasons. Instead, the origin of the domed ambulatory church was partly provincial. One result of this study is that the origin of the Middle Byzantine domed octagonal types was traced to Constantinople. This is attested on the basis of the archaeological evidence. Also some other architectural elements that have not been preserved in the destroyed capital have survived at the provincial level: the domed hexagonal type, the multi-domed superstructure, the pseudo-octagon and the narthex known as the lite. The Constantinopolitan architecture during the period in question was based on the Early Christian and Late Antique forms, practices and innovations and this also emerges at the provincial level.

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This paper presents the architecture and the VHDL design of an integer 2-D DCT used in the H.264/AVC. The 2-D DCT computation is performed by exploiting it’s orthogonality and separability property. The symmetry of the forward and inverse transform is used in this implementation. To reduce the computation overhead for the addition, subtraction and multiplication operations, we analyze the suitability of carry-free position independent residue number system (RNS) for the implementation of 2-D DCT. The implementation has been carried out in VHDL for Altera FPGA. We used the negative number representation in RNS, bit width analysis of the transforms and dedicated registers present in the Logic element of the FPGA to optimize the area. The complexity and efficiency analysis show that the proposed architecture could provide higher through-put.

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This paper presents the architecture of a fault-tolerant, special-purpose multi-microprocessor system for solving Partial Differential Equations (PDEs). The modular nature of the architecture allows the use of hundreds of Processing Elements (PEs) for high throughput. Its performance is evaluated by both analytical and simulation methods. The results indicate that the system can achieve high operation rates and is not sensitive to inter-processor communication delay.

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Verso: Das Gartentor zu Daijas Vaterhaus Georg lebete um die Ecke

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Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. With the requirement to process packets at line rates, high-performance routers need to forward millions of packets every second with each packet needing up to seven memory accesses. Earlier work shows that a single cache for the nodes of a trie can reduce the number of external memory accesses. It is observed that the locality characteristics of the level-one nodes of a trie are significantly different from those of lower level nodes. Hence, we propose a heterogeneously segmented cache architecture (HSCA) which uses separate caches for level-one and lower level nodes, each with carefully chosen sizes. Besides reducing misses, segmenting the cache allows us to focus on optimizing the more frequently accessed level-one node segment. We find that due to the nonuniform distribution of nodes among cache sets, the level-one nodes cache is susceptible t high conflict misses. We reduce conflict misses by introducing a novel two-level mapping-based cache placement framework. We also propose an elegant way to fit the modified placement function into the cache organization with minimal increase in access time. Further, we propose an attribute preserving trace generation methodology which emulates real traces and can generate traces with varying locality. Performanc results reveal that our HSCA scheme results in a 32 percent speedup in average memory access time over a unified nodes cache. Also, HSC outperforms IHARC, a cache for lookup results, with as high as a 10-fold speedup in average memory access time. Two-level mappin further enhances the performance of the base HSCA by up to 13 percent leading to an overall improvement of up to 40 percent over the unified scheme.

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Verso: Possibly the Gottschalk house at Zeppelinstrasse 2 in Hannover, Germany, dated 1911. Removed from an unknown scrapbook.

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In this paper, three parallel polygon scan conversion algorithms have been proposed, and their performance when executed on a shared bus architecture has been compared. It has been shown that the parallel algorithm that does not use edge coherence performs better than those that use edge coherence. Further, a multiprocessing architecture has been proposed to execute the parallel polygon scan conversion algorithms more efficiently than a single shared bus architecture.

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Aenny Catzenstein is seen sitting on a sofa in the left corner of the picture

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