Electrical Properties at Grain Boundaries Influenced by Cr3+ Diffusion in SnO2.ZnO.Nb2O5-Films Varistor Prepared by Electrophoresis Deposition

SnO2-based varistors are strong candidates to replace the ZnO-based varistors due to ordering fewer additives to improve its electrical behavior as well as by showing similar nonlinear characteristics of ZnO varistors. In this work, SnO2-nanoparticles based-varistors with addition of 1.0 %mol of ZnO and 0.05 %mol of Nb2O5 were synthesized by chemical route. SnO2.ZnO.Nb2O5-films with 5 μm of thickness were obtained by electrophoretic deposition (EPD) of the nanoparticles on Si/Pt substrate from alcoholic suspension of SnO2-based powder. The sintering step was carried out in a microwave oven at 1000 °C for 40 minutes. Then, Cr3+ ions were deposited on the films surface by EPD after the sintering step. Each sample was submitted to different thermal treatments to improve the varistor behavior by diffusion of ions in the samples. The films showed a nonlinear coefficient (α) greater than 9, breakdown voltage (VR) around 60 V, low leakage current (IF ≈ 10-6 A), height potential barrier above 0.5 eV and grain boundary resistivity upward of 107 Ω.cm.

Electrophoretic deposition of (Zn, Nb)SnO2-films varistor superficially modified with Cr3+

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Fabrication and structural characterization of bismuth niobate thin films grown by chemical solution deposition

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Heterojunction between Al2O3 and SnO2 thin films for application in transparent FET

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Ferroelectric and dielectric characteristics of Bi3.25La0.75Ti3O12 thin films prepared by the polymeric precursor method

The ferroelectric properties and leakage current mechanisms of preferred oriented Bi3.25La0.75 Ti3O12 (BLT) thin films deposited on La0.5Sr0.5CoO3 (LSCO) by the polymeric precursor method were investigated. Atomic force microscopy indicates that the deposited films exhibit a dense microstructure with a rather smooth surface morphology. The improved ferroelectric and leakage current characteristics can be ascribed to the plate-like grains of the BLT films. © 2006 Trans Tech Publications, Switzerland.

Análise da resposta dielétrica e varistora de compostos cerâmicos multifásicos à base de Ca2CU2Ti4-xSnxO12 (0,0 < x< 4,0)

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Performance of electronic devices submitted to X-rays and high energy proton beams

In this work we have studied the radiation effects on MOSFET electronic devices. The integrated circuits were exposed to 10 key X-ray radiation and 2.6 MeV energy proton beam. We have irradiated MOSFET devices with two different geometries: rectangular-gate transistor and circular-gate transistor. We have observed the cumulative dose provokes shifts on the threshold voltage and increases or decreases the transistor's off-state and leakage current. The position of the trapped charges in modern CMOS technology devices depends on radiation type, dose rate, total dose, applied bias and is a function of device geometry. We concluded the circular-gate transistor is more tolerant to radiation than the rectangular-gate transistor. (C) 2011 Elsevier B.V. All rights reserved.

Detection of partial discharges at field in SF6 insulated equipments

This paper presents the results of research aiming to develop partial discharge detection techniques in high voltage equipment, at substation environment. Measurements of high frequency components of leakage current, at equipments' grounding conductor, were performed. This procedure was performed with the equipment energized and without disconnecting it from the system. The partial discharge generated current pulse is picked up by a high frequency CT, and is detected by an oscilloscope. The partial discharge identification was made considering previously obtained laboratory results, where partial discharges were characterized by means of its time domain signatures. This paper focuses measurements in SF6 circuit breakers. Encouraging results were obtained, showing the feasibility of detecting partial discharges in energized equipment in the laboratory and in the field, in a substation environment, using this method.

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

In situ real-time investigation of Organic Ultra-Thin-Film transistors: growth, electrical properties and biosensing applications

Organic electronics has grown enormously during the last decades driven by the encouraging results and the potentiality of these materials for allowing innovative applications, such as flexible-large-area displays, low-cost printable circuits, plastic solar cells and lab-on-a-chip devices. Moreover, their possible field of applications reaches from medicine, biotechnology, process control and environmental monitoring to defense and security requirements. However, a large number of questions regarding the mechanism of device operation remain unanswered. Along the most significant is the charge carrier transport in organic semiconductors, which is not yet well understood. Other example is the correlation between the morphology and the electrical response. Even if it is recognized that growth mode plays a crucial role into the performance of devices, it has not been exhaustively investigated. The main goal of this thesis was the finding of a correlation between growth modes, electrical properties and morphology in organic thin-film transistors (OTFTs). In order to study the thickness dependence of electrical performance in organic ultra-thin-film transistors, we have designed and developed a home-built experimental setup for performing real-time electrical monitoring and post-growth in situ electrical characterization techniques. We have grown pentacene TFTs under high vacuum conditions, varying systematically the deposition rate at a fixed room temperature. The drain source current IDS and the gate source current IGS were monitored in real-time; while a complete post-growth in situ electrical characterization was carried out. At the end, an ex situ morphological investigation was performed by using the atomic force microscope (AFM). In this work, we present the correlation for pentacene TFTs between growth conditions, Debye length and morphology (through the correlation length parameter). We have demonstrated that there is a layered charge carriers distribution, which is strongly dependent of the growth mode (i.e. rate deposition for a fixed temperature), leading to a variation of the conduction channel from 2 to 7 monolayers (MLs). We conciliate earlier reported results that were apparently contradictory. Our results made evident the necessity of reconsidering the concept of Debye length in a layered low-dimensional device. Additionally, we introduce by the first time a breakthrough technique. This technique makes evident the percolation of the first MLs on pentacene TFTs by monitoring the IGS in real-time, correlating morphological phenomena with the device electrical response. The present thesis is organized in the following five chapters. Chapter 1 makes an introduction to the organic electronics, illustrating the operation principle of TFTs. Chapter 2 presents the organic growth from theoretical and experimental points of view. The second part of this chapter presents the electrical characterization of OTFTs and the typical performance of pentacene devices is shown. In addition, we introduce a correcting technique for the reconstruction of measurements hampered by leakage current. In chapter 3, we describe in details the design and operation of our innovative home-built experimental setup for performing real-time and in situ electrical measurements. Some preliminary results and the breakthrough technique for correlating morphological and electrical changes are presented. Chapter 4 meets the most important results obtained in real-time and in situ conditions, which correlate growth conditions, electrical properties and morphology of pentacene TFTs. In chapter 5 we describe applicative experiments where the electrical performance of pentacene TFTs has been investigated in ambient conditions, in contact to water or aqueous solutions and, finally, in the detection of DNA concentration as label-free sensor, within the biosensing framework.

Rastertunnelmikroskopie kombiniert mit optischen Methoden und ihre Anwendung für opto-elektronische Experimente an nanoskopischen Strukturen

Die vorliegende Arbeit untersucht mittels lichtunterstützter Tunnelmikroskopie (STM) den Elektronentransport in farbstoffbedeckten, nanoporösen TiO2-Schichten, die in photoelektrochemischen Solarzellen eingesetzt werden. Transportrelevante Eigenschaften wie die elektronische Zustandsdichte sowie lichtinduzierte Vorgänge wie der Aufbau einer lichtinduzierten Oberflächenladung und lokale Photoströme werden ortsaufgelöst gemessen. Für einen möglichen Einsatz in lichtunterstützter Tunnelmikroskopie werden desweiteren Gold-Nanopartikel auf einer Amino-Hexanthiol-Monolage auf Coulomb-Blockaden untersucht. Den zweite Schwerpunkt stellen methodische Arbeiten zur Messung optischer Nahfelder in STM-Experimenten dar. Erstens sollen die Vorteile von Apertur- und aperturloser optischer Rasternahfeld-Mikroskopie mit komplett metallisierten Faserspitzen verbunden werden, die durch die Faser beleuchtet werden. Es gelingt nicht, theoretisch vorhergesagte hohe optische Auflösungen zu bestätigen. Zweitens werden transparente Spitzen aus Sb-dotiertem Zinnoxid erfolgreich als Tunnelspitzen getestet. Die Spitzen ermöglichen STM-Elektrolumineszenz-Experimente zur Charakterisierung optischer Nahfelder, ohne diese durch eine metallische Spitze zu beeinträchtigen. In einer STM-Studie wird das Selbstorganisations-Verhalten von Oktanthiol und Oktandithiol auf Au(111) aus Ethanol untersucht. Bei geringer relativer Konzentration der Dithiole (1:2000), bildet sich eine Phase liegender Dithiole, deren Ordnung durch die Präsenz der Oktanthiole katalysiert wird. Schließlich wird ein als 'dynamische Tunnelmikroskopie' bezeichneter Modus für die Tunnelmikroskopie in elektrisch leitfähiger Umgebung erfolgreich getestet, der zur Unterdrückung des elektrochemischen Leckstromanteils die Ableitung des Stroms nach dem Abstand als STM-Abstandssignal verwendet.

Characterization of HFO2 Capacitors

Hafnium oxide (HfOn) is a promising dielectric for future microelectronic applications. Hf02 thin films (10-75nm) were deposited on Pt/Si02/Si substrates by pulsed DC magnetron reactive sputtering. Top electrodes of Pt were formed by e-beam evapo- ration through an aperture mask on the samples to create MIM (Metal-Insulator-Metal) capacitors. Various processing conditions (Arloz ratio, DC power and deposition rate) and post-deposition annealing conditions (time and temperature) were investigated. The structure of the Hf02 films was characterized by X-ray diffraction (XRD) and the roughness was measured by a profilometer. The electrical properties were characterized in terms of their relative permittivity (E,(T) and ~,.(f)) and leakage behavior (I-V, I-T and I- time). The electrical measurements were performed over a temperature range from -5 to 200°C. For the samples with best experimental results, the relative permittivity of HfOa was found to be -- 27 after anneal and increased by 0.027%/"C with increasing temperature over the measured temperature range. At 25"C, leakage current density was below lop8 ~ l c m ' at 1 volt. The leakage current increased with temperature above a specific threshold temperature below which the leakage current didn't change much. The leakage current increased with voltage. At voltages below lvolt, it's ohmic; at higher voltages, it follows Schottky model. The breakdown field is - 1 . 8 2 ~ lo6 Vlcm. The optical bandgap was measured with samples deposited on quartz substrates to be 5.4eV after anneal.

Role of surface trap states on two-dimensional electron gas density in InAlN/AlN/GaN heterostructures

In order to clarify the effect of charged dislocations and surface donor states on the transport mechanisms in polar AlInN/AlN/GaN heterostructures, we have studied the current-voltage characteristics of Schottky junctions fabricated on AlInN/AlN/GaN heterostructures. The reverse-bias leakage current behaviour has been interpreted with a Poole-Frenkel emission of electrons from trap states near the metal-semiconductor junction to dislocation induced states. The variation of the Schottky barrier height as a function of the AlN layer thickness has been measured and discussed, considering the role of the surface states in the formation of the two dimensional electron gas at AlN/GaN interface.

Ratio-based temperature-sensing technique hardened against nanometer process variations

This letter presents a temperature-sensing technique on the basis of the temperature dependency of MOSFET leakage currents. To mitigate the effects of process variation, the ratio of two different leakage current measurements is calculated. Simulations show that this ratio is robust to process spread. The resulting sensor is quite small-0.0016 mm2 including an analog-to-digital conversion-and very energy efficient, consuming less than 640 pJ/conversion. After a two-point calibration, the accuracy in a range of 40°C-110°C is less than 1.5°C , which makes the technique suitable for thermal management applications.

Temperature performance of AlGaN/GaN MOS-HEMTs on Si substrates using Gd2O3 as gate dielectric

GaN based high electron mobility transistors have draw great attention due to its potential in high temperature, high power and high frequency applications [1, 2]. However, significant gate leakage current is still one of the issues which need to be solved to improve the performance and reliability of the devices [3]. Several research groups have contributed to solve this problem by using metal–oxide–semiconductor HEMTs (MOSHEMTs), with a thin dielectric layer, such as SiO2 [4], Al2O3 [5], HfO2 [6] and Gd2O3 [7] between the gate and the barrier layer on AlGaN/GaN heterostructures. Gd2O3 has shown low interfacial density of states(Dit) with GaN and a high dielectric constant and low electrical leakage currents [8], thus is considered as a promising candidate for the gate dielectrics on GaN. MOS-HEMTs using Gd2O3 grown by electron-beam heating [7] or molecular beam epitaxy (MBE) [8] on GaN or AlGan/GaN structure have been investigated, but further research is still needed in Gd2O3 based AlGaN/GaN MOSHEMTs.