Job phasing aware preemption deferral

Preemptions account for a non-negligible overhead during system execution. There has been substantial amount of research on estimating the delay incurred due to the loss of working sets in the processor state (caches, registers, TLBs) and some on avoiding preemptions, or limiting the preemption cost. We present an algorithm to reduce preemptions by further delaying the start of execution of high priority tasks in fixed priority scheduling. Our approaches take advantage of the floating non-preemptive regions model and exploit the fact that, during the schedule, the relative task phasing will differ from the worst-case scenario in terms of admissible preemption deferral. Furthermore, approximations to reduce the complexity of the proposed approach are presented. Substantial set of experiments demonstrate that the approach and approximations improve over existing work, in particular for the case of high utilisation systems, where savings of up to 22% on the number of preemption are attained.

Trends Of CPU, GPU and FPGA for high-performance computing

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).

Efficient feature selection filters for high-dimensional data

Feature selection is a central problem in machine learning and pattern recognition. On large datasets (in terms of dimension and/or number of instances), using search-based or wrapper techniques can be cornputationally prohibitive. Moreover, many filter methods based on relevance/redundancy assessment also take a prohibitively long time on high-dimensional. datasets. In this paper, we propose efficient unsupervised and supervised feature selection/ranking filters for high-dimensional datasets. These methods use low-complexity relevance and redundancy criteria, applicable to supervised, semi-supervised, and unsupervised learning, being able to act as pre-processors for computationally intensive methods to focus their attention on smaller subsets of promising features. The experimental results, with up to 10(5) features, show the time efficiency of our methods, with lower generalization error than state-of-the-art techniques, while being dramatically simpler and faster.

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia

Simulation of rectifier voltage malfunction on OWECS, four-level converter, HVDC light link: Smart grid context tool

This paper presents a model for the simulation of an offshore wind system having a rectifier input voltage malfunction at one phase. The offshore wind system model comprises a variable-speed wind turbine supported on a floating platform, equipped with a permanent magnet synchronous generator using full-power four-level neutral point clamped converter. The link from the offshore floating platform to the onshore electrical grid is done through a light high voltage direct current submarine cable. The drive train is modeled by a three-mass model. Considerations about the smart grid context are offered for the use of the model in such a context. The rectifier voltage malfunction domino effect is presented as a case study to show capabilities of the model. (C) 2015 Elsevier Ltd. All rights reserved.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.

Simulation of wave action on a moored container carrier inside Sines’ Harbour

The integrated numerical tool SWAMS (Simulation of Wave Action on Moored Ships) is used to simulate the behavior of a moored container carrier inside Sines’ Harbour. Wave, wind, currents, floating ship and moorings interaction is discussed. Several case scenarios are compared differing in the layout of the harbour and wind and wave conditions. The several harbour layouts correspond to proposed alternatives for the future expansion of Sines’ terminal XXI that include the extension of the East breakwater and of the quay. Additionally, the influence of wind on the behavior of the ship moored and the introduction of pre tensioning the mooring lines was analyzed. Hydrodynamic forces acting on the ship are determined using a modified version of the WAMIT model. This modified model utilizes the Haskind relations and the non-linear wave field inside the harbour obtained with finite element numerical model, BOUSS-WMH (Boussinesq Wave Model for Harbors) to get the wave forces on the ship. The time series of the moored ship motions and forces on moorings are obtained using BAS solver. © 2015 Taylor & Francis Group, London.

Parallel GPU architecture for hyperspectral unmixing based on augmented Lagrangian method

Hyperspectral imaging has become one of the main topics in remote sensing applications, which comprise hundreds of spectral bands at different (almost contiguous) wavelength channels over the same area generating large data volumes comprising several GBs per flight. This high spectral resolution can be used for object detection and for discriminate between different objects based on their spectral characteristics. One of the main problems involved in hyperspectral analysis is the presence of mixed pixels, which arise when the spacial resolution of the sensor is not able to separate spectrally distinct materials. Spectral unmixing is one of the most important task for hyperspectral data exploitation. However, the unmixing algorithms can be computationally very expensive, and even high power consuming, which compromises the use in applications under on-board constraints. In recent years, graphics processing units (GPUs) have evolved into highly parallel and programmable systems. Specifically, several hyperspectral imaging algorithms have shown to be able to benefit from this hardware taking advantage of the extremely high floating-point processing performance, compact size, huge memory bandwidth, and relatively low cost of these units, which make them appealing for onboard data processing. In this paper, we propose a parallel implementation of an augmented Lagragian based method for unsupervised hyperspectral linear unmixing on GPUs using CUDA. The method called simplex identification via split augmented Lagrangian (SISAL) aims to identify the endmembers of a scene, i.e., is able to unmix hyperspectral data sets in which the pure pixel assumption is violated. The efficient implementation of SISAL method presented in this work exploits the GPU architecture at low level, using shared memory and coalesced accesses to memory.

Fast unsupervised technique for extraction of endmembers spectra from hyperspectral data

One of the most challenging task underlying many hyperspectral imagery applications is the linear unmixing. The key to linear unmixing is to find the set of reference substances, also called endmembers, that are representative of a given scene. This paper presents the vertex component analysis (VCA) a new method to unmix linear mixtures of hyperspectral sources. The algorithm is unsupervised and exploits a simple geometric fact: endmembers are vertices of a simplex. The algorithm complexity, measured in floating points operations, is O (n), where n is the sample size. The effectiveness of the proposed scheme is illustrated using simulated data.

Aplicação da metodologia SMED numa linha de envernizamento/pintura de revestimentos de cortiça

O presente trabalho visa a redução do tempo de mudança de produção e consequente aumento de produtividade de uma linha de envernizamento/pintura integrada na empresa Amorim Revestimentos SA, unidade S. Paio de Oleiros, que se dedica à produção de pisos flutuantes. Esta necessidade surgiu pelo facto desta linha de produção ser um ponto de estrangulamento do processo produtivo no departamento em que está inserida, devido principalmente à diminuição do tamanho de lotes e aumento da variedade de artigos a produzir. O trabalho envolveu as várias etapas da ferramenta SMED às quais está inerente a aplicação da técnica 5S às máquinas e ferramentas garantindo, assim, o posto de trabalho arrumado, limpo, seguro e com tudo pronto a ser utilizado. Aplicou-se a ferramenta SMED a dois tipos de mudança de acabamento e à mudança de rolo de pintura. Após a implementação desta ferramenta verificou-se uma redução de tempos de 37% (48 para 30 minutos) na mudança de pintura e acabamento de verniz, reduziu-se 25% (32 para 24 minutos) na mudança só de pintura e 13% (46 para 40 minutos) na mudança de rolo de pintura. Estes resultados foram alcançados através da redução do tempo das tarefas externas e internas e transformação das tarefas internas em externas consequentes da aplicação de um conjunto de ações de melhorias. Também foi fundamental a alteração do método de trabalho e a organização geral do posto de trabalho, no que diz respeito à repartição equilibrada das tarefas pelos dois operadores, alteração do sequenciamento das tarefas e aplicação da técnica 5S. As soluções encontradas estão sendo monitorizadas através do registo efectuado pelos operadores e realização de auditorias internas para garantir a perpetuação dos resultados.

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e Tecnologia

Desenvolvimento de um robô com pernas inspirado no Alfaiate

A elaboração deste trabalho surge no âmbito da unidade curricular de Tese/Dissertação, integrada no Mestrado em Engenharia Eletrotécnica e de Computadores do Instituto Superior de Engenharia do Porto. O trabalho enquadra-se no âmbito da robótica de inspiração biológica, mais concretamente no desenvolvimento de um robô que apresente caraterísticas de locomoção similares ao inseto Alfaiate, modificando para este efeito um robô hexápode já existente. Inicialmente efetuou-se um estudo sobre a biologia do Alfaiate e dos vários tipos de padrões de locomoção adotados pelos animais. De seguida foi realizado um estudo sobre alguns robôs já existentes inspirados neste inseto. Após a realização desta fase de estudo, foram implementadas modificações ao robô hexápode, de forma a este conseguir apoiar-se e movimentar-se sobre a superfície da água. Para tal foram utilizados apoios em esferovite para as pernas, servomotores para a atuação e um sensor de IRPD para orientar o robô na sua trajetória. Em termos de controlo da estabilidade do corpo utilizou-se um giroscópio para permitir ao robô manter o seu corpo horizontal durante a locomoção em águas agitadas. Este trabalho termina com a realização de testes a diferentes padrões de locomoção, de forma a validar o que apresenta a melhor resposta em termos de velocidade.

Toxocara spp. eggs in public squares of Sorocaba, São Paulo State, Brazil

The visceral larva migrans (VLM) is a syndrome observed in human infection with helminth larval eggs such as the Toxocara spp. that usually infects dogs and cats. Among the risk factors involved in the occurrence of VLM, particularly important is the size of these animal populations. Sorocaba is a city with a dog population twice as large as that recommended by the World Health Organization. This fact has led to a survey of the presence of Toxocara spp. eggs in public square soils of this city. Thirty squares were selected, fifteen located in the outskirts of the city and fifteen downtown. Soil samples were collected from five distinct sites in the same area. The material was homogenized and drained and 100 g was mixed with a saturated solution of magnesium sulfate and 5% potassium iodine. The floating material was analyzed under the light microscope. Toxocara spp. eggs were found in 16 squares, nine of which were located in the outskirts of the city and seven downtown. It was concluded that Sorocaba squares present a high rate of contamination with Toxocara spp. eggs. The squares in the outskirts of the city presented a higher occurrence of these eggs in comparison with those downtown, although the difference was not statistically significant (p > 0.05).

Design and Implementation of a Biologically Inspired Swimming Robot - An EPS@ISEP 2014 Spring Project

This paper presents the development of a fish-like robot called Bro-Fish. Bro-Fish aims to be an educational toy dedicated to teaching mechanics, programming and the physics of floating objects to youngsters. The underlying intention is to awaken the interest of children for technology, especially biomimetic (biologically inspired) approaches, in order to promote sustainability and raise the level of ecological awareness. The main focus of this project was to create a robot with carangiform locomotion and controllable swimming, providing the opportunity to customize parts and experiment with the physics of floating objects. Therefore, the locomotion principles of fishes and mechanisms developed in related projects were analysed. Inspired by this background knowledge, a prototype was designed and implemented. The main achievement is the new tail mechanism that propels the robot. The tail resembles the undulation motion of fish bodies and is actuated in an innovative way, triggered by an elegant movement of a rotating helicoidal. First experimental tests revealed the potential of the proposed methodology to effectively generate forward propulsion.