Electrical switching studies on AS(40)Te(60-x)Se(x) and As35Te65-xSex glasses

The I-V characteristics of bulk As40Te60-xSex and As35Te65-xSex glasses have been studied with a current sweep of 0-18 mA-0, over a wide range of compositions (4 less than or equal to x less than or equal to 22). All the glasses studied showed a threshold electrical switching behaviour. The number of switching cycles withstood by the samples has been found to depend on the ON-state current. It is seen that the switching voltages increase with increase in selenium content. Further, the switching voltages are found to be almost independent of the thickness of the sample (d), in the range 0.18-0.3 mm. Also, the switching voltages and the number of switching cycles withstood by the samples are found to decrease with temperature.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

Hybrid LCI/VSI Power Circuit-A Universal High-Power Converter Solution for Wound Field Synchronous Motor Drives

Load commutated inverter (LCI)-fed wound field synchronous motor drives are used for medium-voltage high-power drive applications. This drive suffers from drawbacks such as complex starting procedure, sixth harmonic torque pulsations, quasi square wave motor current, notches in the terminal voltages, etc. In this paper, a hybrid converter circuit, consisting of an LCI and a voltage source inverter (VSI), is proposed, which can be a universal high-power converter solution for wound field synchronous motor drives. The proposed circuit, with the addition of a current-controlled VSI, overcomes nearly all of the shortcomings present in the conventional LCI-based system besides providing many additional advantages. In the proposed drive, the motor voltage and current are always sinusoidal even with the LCI switching at the fundamental frequency. The performance of the drive is demonstrated with detailed experimental waveforms from a 15.8-hp salient pole wound field synchronous machine. Finally, a brief description of the control scheme used for the proposed circuit is given.

Potential and Electric Field Profiles for Transmission line Insulators

Transmission of bulk power at high voltages over very long distances has become very imperative. At present, throughout the globe, this task has been mostly performed by overhead transmission lines. The dual task of mechanically supporting and electrically isolating the live phase conductors from the support tower is performed by string insulators. Whether in clean condition or under polluted conditions, the electrical stress distribution along the insulators governs the possible flashover, which is quite detrimental to the system. However, a reliable data on stress distribution in commonly employed string insulators are rather scarce. Considering this, the present work has made an attempt to study accurately, the field distribution in 220 kV strings for six different types of porcelain/ceramic insulators (Normal and Antifog discs) used for high voltage transmission. The surface charge simulation method is employed for the required field computation. Voltage and electric stress distribution is deduced and compared across different types of discs. A comparison on normalised surface resistance, which is an indicator for the stress concentration under polluted condition, is also attempted.

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations

Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.

Coupling of High Voltage AC Power Line Fields to Metallic Pipelines

In the recent years, there has been a trend to run metallic pipelines carrying petroleum products and high voltage AC power lines parallel to each other in a relatively narrow strip of land. Due to this sharing of the right-of-way, verhead AC power line electric field may induce voltages on the metallic pipelines running in close vicinity leading to serious adverse effects. In this paper, the induced voltages on metallic pipelines running in close vicinity of high voltage power transmission lines have been computed. Before computing the induced voltages, an optimum configuration of the phase conductors based on the lowest conductor surface gradient and field under transmission line has been arrived at. This paper reports the conductor surface field gradients calculated for the various configurations. Also the electric fields under transmission line, for single circuit and double circuit (various phase arrangements) have been analyzed. Based on the above results, an optimum configuration giving the lowest field under the power line as well as the lowest conductor surface gradient has been arrived at and for this configuration, induced voltage on the pipeline has been computed using the Charge Simulation Method (CSM). For comparison, induced voltages on the pipeline has been computed for the various other phase configurations also.

Spin-polarized STM spectra of Dirac electrons on the surface of a topological insulator

We provide a theory for the tunneling conductance G(V) of Dirac electrons on the surface of a topological insulator as measured by a spin-polarized scanning tunneling microscope tip for low-bias voltages V. We show that if the in-plane rotational symmetry on the surface of the topological insulator is broken by an external field that does not couple to spin directly (such as an in-plane electric field), G(V) exhibits an unconventional dependence on the direction of the magnetization of the tip, i.e., it acquires a dependence on the azimuthal angle of the magnetization of the tip. We also show that G(V) can be used to measure the magnitude of the local out-of-plane spin orientation of the Dirac electrons on the surface. We explain the role of the Dirac electrons in this unconventional behavior and suggest experiments to test our theory.

A Sensor for Sulfur Gas Based on Silver β-Alumina

EMF measurements were made with an electrochemical cell of the type ~t/&(s)/&+-beta alumina/Ag~S(s)S. 2(g). S(s or 1)/R at temperatures between 95 and 241°C. Sflver $- alumina was prepared with the ion exchange technique. The patial pressure of diatomic gas obtained from cell voltages agreed with the literature data.

Substrate nitridation induced modulations in transport properties of wurtzite GaN/p-Si (100) heterojunctions grown by molecular beam epitaxy

Phase pure wurtzite GaN films were grown on Si (100) substrates by introducing a silicon nitride layer followed by low temperature GaN growth as buffer layers. GaN films grown directly on Si (100) were found to be phase mixtured, containing both cubic (beta) and hexagonal (alpha) modifications. The x-ray diffraction (XRD), scanning electron microscopy (SEM), photoluminescence (PL) spectroscopy studies reveal that the significant enhancement in the structural as well as in the optical properties of GaN films grown with silicon nitride buffer layer grown at 800 degrees C when compared to the samples grown in the absence of silicon nitride buffer layer and with silicon nitride buffer layer grown at 600 degrees C. Core-level photoelectron spectroscopy of Si(x)N(y) layers reveals the sources for superior qualities of GaN epilayers grown with the high temperature substrate nitridation process. The discussion has been carried out on the typical inverted rectification behavior exhibited by n-GaN/p-Si heterojunctions. Considerable modulation in the transport mechanism was observed with the nitridation conditions. The heterojunction fabricated with the sample of substrate nitridation at high temperature exhibited superior rectifying nature with reduced trap concentrations. Lowest ideality factors (similar to 1.5) were observed in the heterojunctions grown with high temperature substrate nitridation which is attributed to the recombination tunneling at the space charge region transport mechanism at lower voltages and at higher voltages space charge limited current conduction is the dominating transport mechanism. Whereas, thermally generated carrier tunneling and recombination tunneling are the dominating transport mechanisms in the heterojunctions grown without substrate nitridation and low temperature substrate nitridation, respectively. (C) 2011 American Institute of Physics. [doi:10.1063/1.3658867]

Low‐voltage varistors based on zinc antimony spinel Zn7Sb2O12

It is possible to prepare low‐voltage varistors from the zinc antimony spinel Zn7Sb2O12 with breakdown voltages in the range of 3–20 V and nonlinearity coefficient α=7–15. The varistor property is due to the formation of high ohmic potential barriers at the grain boundary regions on low‐ohmic n‐type grain interiors of the polycrystalline samples. The method of preparation of the spinel, synthesized by coprecipitation followed by annealing under restricted partial pressures of oxygen, controls the mixed valence states for antimony, namely, Sb3+ and Sb5+. This is critical in attaining high nonlinearity and lower breakdown voltages.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Growth and characterization of SrBi2Nb2O9 thin films by pulsed-laser ablation

Polycrystalline films of SrBi2Nb2O9 were grown using pulsed-laser ablation. The ferroelectric properties were achieved by low-temperature deposition followed by a subsequent annealing process. The lower switching voltage was obtained by lowering the thickness, which did not affect the insulating nature of the films. The hysteresis results showed an excellent square-shaped loop with results (Pr = 6 μC/cm2, Ec = 100 kV/cm) in good agreement with earlier reports. The films also exhibited a dielectric constant of 250 and a dissipation factor of 0.02. The transport studies indicated an ohmic behavior, while higher voltages induced a bulk space charge.

A hybrid nine-level inverter for IM drive

This paper proposes a new hybrid nine-level inverter topology for IM drive. The nine-level structure is realized by using two three-phase two-level inverters fed by isolated DC voltage sources and six H-bridges fed by capacitors. The number of switches required in this topology is only 36 where as the conventional nine-level topologies require 48 switches. The voltages across the capacitors, feeding the H-bridges that operate at asymmetric voltages, are effectively balanced by making use of the switching state redundancies. In this topology, the requirement of DC link voltage is only half of the maximum magnitude of the voltage space vector. As the two-level inverters are powered by isolated voltage sources, the circulation of triplen harmonic current in the motor winding is prevented. The proposed drive system is capable of functioning in three-level mode in case of any switch failure in H-bridges. The performance of the proposed topology in the entire modulation range is verified by simulation study and experiment.

Thermodynamic, kinetic and electrical switching studies on Si(15)Te(85-x)In(x) glasses: Observation of Boolchand intermediate phase

An interesting topic for quite some time is an intermediate phase observed in chalcogenide glasses, which is related to network connectivity and rigidity. This phenomenon is exhibited by Si-Te-In glasses also. It has been addressed here by carrying out detailed thermal investigations by using Alternating Differential Scanning Calorimetry technique. An effort has also been made to determine the stability of these glasses using the data obtained from different thermodynamic quantities and crystallization kinetics of these glasses. Electrical switching behavior by recording I-V characteristics and variation of switching voltages with indium composition have been studied in these glasses for phase change memory applications. (C) 2011 Elsevier Inc. All rights reserved.