Low Mass Calibration Target for MM-Wave Remote Sensing Instruments

The reliability of millimeter and sub-millimeter wave radiometer measurements is dependent on the accuracy of the loads they employ as calibration targets. In the recent past on-board calibration loads have been developed for a variety of satellite remote sensing instruments. Unfortunately some of these have suffered from calibration inaccuracies which had poor thermal performance of the calibration target as the root cause. Stringent performance parameters of the calibration target such as low reflectivity, high temperature uniformity, low mass and low power consumption combined with low volumetric requirements remain a challenge for the space instrument developer. In this paper we present a novel multi-layer absorber concept for a calibration load which offers an excellent compromise between very good radiometric performance and temperature uniformity and the mass and volumetric constraints required by space-borne calibration targets.

Oxygen-transfer performance of a newly designed, very low-volume membrane oxygenator.

OBJECTIVES Oxygenation of blood and other physiological solutions are routinely required in fundamental research for both in vitro and in vivo experimentation. However, very few oxygenators with suitable priming volumes (<2-3 ml) are available for surgery in small animals. We have designed a new, miniaturized membrane oxygenator and investigated the oxygen-transfer performance using both buffer and blood perfusates. METHODS The mini-oxygenator was designed with a central perforated core-tube surrounded by parallel-oriented microporous polypropylene hollow fibres, placed inside a hollow shell with a lateral-luer outlet, and sealed at both extremities. With this design, perfusate is delivered via the core-tube to the centre of the mini-oxygenator, and exits via the luer port. A series of mini-oxygenators were constructed and tested in an in vitro perfusion circuit by monitoring oxygen transfer using modified Krebs-Henseleit buffer or whole porcine blood. Effects of perfusion pressure and temperature over flows of 5-60 ml × min(-1) were assessed. RESULTS Twelve mini-oxygenators with a mean priming volume of 1.5 ± 0.3 ml were evaluated. With buffer, oxygen transfer reached a maximum of 14.8 ± 1.0 ml O2 × l(-1) (pO2: 450 ± 32 mmHg) at perfusate flow rates of 5 ml × min(-1) and decreased with an increase in perfusate flow to 7.8 ± 0.7 ml ml O2 × l(-1) (pO2: 219 ± 24 mmHg) at 60 ml × min(-1). Similarly, with blood perfusate, oxygen transfer also decreased as perfusate flow increased, ranging from 33 ± 5 ml O2 × l(-1) at 5 ml × min(-1) to 11 ± 2 ml O2 × l(-1) at 60 ml × min(-1). Furthermore, oxygen transfer capacity remained stable with blood perfusion over a period of at least 2 h. CONCLUSIONS We have developed a new miniaturized membrane oxygenator with an ultra-low priming volume (<2 ml) and adequate oxygenation performance. This oxygenator may be of use in overcoming current limitations in equipment size for effective oxygenation in low-volume perfusion circuits, such as small animal extracorporeal circulation and ex vivo organ perfusion.

Oxygen-transfer performance of a newly designed, very low-volume membrane oxygenator

Gebiet: Chirurgie Biomedizintechnik Biophysik Transplantationsmedizin Kardiologie Abstract: OBJECTIVES: – Oxygenation of blood and other physiological solutions are routinely required in fundamental research for both in vitro and in vivo experimentation. However, very few oxygenators with suitable priming volumes (<2-3 ml) are available for surgery in small animals. We have designed a new, miniaturized membrane oxygenator and investigated the oxygen-transfer performance using both buffer and blood perfusates. – – METHODS: – The mini-oxygenator was designed with a central perforated core-tube surrounded by parallel-oriented microporous polypropylene hollow fibres, placed inside a hollow shell with a lateral-luer outlet, and sealed at both extremities. With this design, perfusate is delivered via the core-tube to the centre of the mini-oxygenator, and exits via the luer port. A series of mini-oxygenators were constructed and tested in an in vitro perfusion circuit by monitoring oxygen transfer using modified Krebs-Henseleit buffer or whole porcine blood. Effects of perfusion pressure and temperature over flows of 5-60 ml × min(-1) were assessed. – – RESULTS: – Twelve mini-oxygenators with a mean priming volume of 1.5 ± 0.3 ml were evaluated. With buffer, oxygen transfer reached a maximum of 14.8 ± 1.0 ml O2 × l(-1) (pO2: 450 ± 32 mmHg) at perfusate flow rates of 5 ml × min(-1) and decreased with an increase in perfusate flow to 7.8 ± 0.7 ml ml O2 × l(-1) (pO2: 219 ± 24 mmHg) at 60 ml × min(-1). Similarly, with blood perfusate, oxygen transfer also decreased as perfusate flow increased, ranging from 33 ± 5 ml O2 × l(-1) at 5 ml × min(-1) to 11 ± 2 ml O2 × l(-1) at 60 ml × min(-1). Furthermore, oxygen transfer capacity remained stable with blood perfusion over a period of at least 2 h. – – CONCLUSIONS: – We have developed a new miniaturized membrane oxygenator with an ultra-low priming volume (<2 ml) and adequate oxygenation performance. This oxygenator may be of use in overcoming current limitations in equipment size for effective oxygenation in low-volume perfusion circuits, such as small animal extracorporeal circulation and ex vivo organ perfusion. – – © The Author 2015. Published by Oxford University Press on behalf of the European Association for Cardio-Thoracic Surgery. All rights reserved.

The Face of Power

Objective: In humans and other animals, open, expansive postures (compared to contracted postures) are evolutionary developed expressions of power and have been shown to cause neuroendocrine and behavioral changes (Carney, Cuddy, & Yap, 2010). In the present study we aimed to investigate whether power postures have a bearing on the participant’s facial appearance and whether others are able to distinguish faces after “high power posing” from faces after “low power posing”. Methods: 16 models were photographed 4-5 minutes after having adopted high and low power postures. Two different high power and two different low power postures were held for 2 minutes each. Power-posing sessions were performed on two consecutive days. High and low power photographs of each model were paired and an independent sample of 100 participants were asked to pick the more dominant and the more likeable face of each pair. Results: Photographs that were taken after adopting high power postures were chosen significantly more often as being more dominant looking. There was no preference when asked to choose the more likeable photograph (chance level). A further independent sample rated each photograph for head tilt, making it unlikely that dominance ratings were caused merely by the posture of the head. Consistently, facial width-to-height ratio did not differ between faces after high and low power posing. Conclusions: Postures associated with high power affect facial appearance, leading to a more dominant looking face. This finding may have implications for everyday life, for instance when a dominant appearance is needed.

Impact of N2 plasma power and duration on AlGaN/GaN HEMT

urface treatments have been recently shown to play an active role in electrical characteristics in AlGaN/GaN HEMTs, in particular during the passivation processing [1-4]. However, the responsible mechanisms are partially unknown and further studies are demanding. The effects of power and time N2 plasma pre-treatment prior to SiN deposition using PE-CVD (plasma enhanced chemical vapour deposition) on GaN and AlGaN/GaN HEMT have been investigated. The low power (60 W) plasma pre-treatment was found to improve the electronic characteristics in GaN based HEMT devices, independently of the time duration up to 20 min. In contrast, high power (150 and 210 W) plasma pretreatment showed detrimental effects in the electronic properties (Fig. 1), increasing the sheet resistance of the 2DEG, decreasing the 2DEG charge density in AlGaN/GaN HEMTs, transconductance reduction and decreasing the fT and fmax values up to 40% respect to the case using 60 W N2 plasma power. Although AFM (atomic force microscopy) results showed AlGaN and GaN surface roughness is not strongly affected by the N2-plasma, KFM (Kelvin force microscopy) surface analysis shows significant changes in the surface potential, trending to increase its values as the plasma power is higher. The whole results point at energetic ions inducing polarization-charge changes that affect dramatically to the 2-DEG charge density and the final characteristics of the HEMT devices. Therefore, we conclude that AlGaN surface is strongly sensitive to N2 plasma power conditions, which turn to be a key factor to achieve a good surface preparation prior to SiN passivation.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Power management techniques in an FPGA-Based WSN node for high performance application

In this work, the power management techniques implemented in a high-performance node for Wireless Sensor Networks (WSN) based on a RAM-based FPGA are presented. This new node custom architecture is intended for high-end WSN applications that include complex sensor management like video cameras, high compute demanding tasks such as image encoding or robust encryption, and/or higher data bandwidth needs. In the case of these complex processing tasks, yet maintaining low power design requirements, it can be shown that the combination of different techniques such as extensive HW algorithm mapping, smart management of power islands to selectively switch on and off components, smart and low-energy partial reconfiguration, an adequate set of save energy modes and wake up options, all combined, may yield energy results that may compete and improve energy usage of typical low power microcontrollers used in many WSN node architectures. Actually, results show that higher complexity tasks are in favor of HW based platforms, while the flexibility achieved by dynamic and partial reconfiguration techniques could be comparable to SW based solutions.

Loss model for a high frequency and low load DC/DC synchronous buck converter

This work presents a behavioral-analytical hybrid loss model for a buck converter. The model has been designed for a wide operating frequency range up to 4MHz and a low power range (below 20W). It is focused on the switching losses obtained in the power MOSFETs. Main advantages of the model are the fast calculation time and a good accuracy. It has been validated by simulation and experimentally with one Ga, power transistor and two Si MOSFETs. Results show good agreement between measurements and the model.

Hybrid behavioral-analytical loss model for a high frequency and low load DC/DC buck converter

This work presents a behavioral-analytical hybrid loss model for a buck converter. The model has been designed for a wide operating frequency range up to 4MHz and a low power range (below 20W). It is focused on the switching losses obtained in the power MOSFETs. Main advantages of the model are the fast calculation time (below 8.5 seconds) and a good accuracy, which makes this model suitable for the optimization process of the losses in the design of a converter. It has been validated by simulation and experimentally with one GaN power transistor and three Si MOSFETs. Results show good agreement between measurements and the model

Impact of N2 plasma power discharge on AlGaN/GaN HEMT performance

The effects of power and time conditions of in situ N2 plasma treatment, prior to silicon nitride (SiN) passivation, were investigated on an AlGaN/GaN high-electron mobility transistor (HEMT). These studies reveal that N2 plasma power is a critical parameter to control the SiN/AlGaN interface quality, which directly affects the 2-D electron gas density. Significant enhancement in the HEMT characteristics was observed by using a low power N2 plasma pretreatment. In contrast, a marked gradual reduction in the maximum drain-source current density (IDS max) and maximum transconductance (gm max), as well as in fT and fmax, was observed as the N2 plasma power increases (up to 40% decrease for 210 W). Different mechanisms were proposed to be dominant as a function of the discharge power range. A good correlation was observed between the device electrical characteristics and the surface assessment by atomic force microscopy and Kelvin force microscopy techniques.

Optimization and evaluation in space conditions of multi-GHz optical modulators

Among the different optical modulator technologies available such as polymer, III-V semiconductors, Silicon, the well-known Lithium Niobate (LN) offers the best trade-off in terms of performances, ease of use, and power handling capability [1-9]. The LN technology is still widely deployed within the current high data rate fibre optic communications networks. This technology is also the most mature and guarantees the reliability which is required for space applications [9].In or der to fulfil the target specifications of opto-microwave payloads, an optimization of the design of a Mach-Zehnder (MZ) modulator working at the 1500nm telecom wavelength was performed in the frame of the ESA-ARTES "Multi GigaHertz Optical Modulator" (MGOM) project in order to reach ultra-low optical insertion loss and low effective driving voltage in the Ka band. The selected modulator configuration was the X-cut crystal orientation, associated to high stability Titanium in-diffusion process for the optical waveguide. Starting from an initial modulator configuration exhibiting 9 V drive voltage @ 30 GHz, a complete redesign of the coplanar microwave electrodes was carried out in order to reach a 6 V drive voltage @ 30GHz version. This redesign was associated to an optimization of the interaction between the optical waveguide and the electrodes. Following the optimisation steps, an evaluation program was applied on a lot of 8 identical modulators. A full characterisation was carried out to compare performances, showing small variations between the initial and final functional characteristics. In parallel, two similar modulators were submitted to both gamma (10-100 krad) and proton irradiation (10.109 p/cm²) with minor performance degradation.

Power-Aware Multi-Objective Evolvable Hardware System on an FPGA

Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The objective of the evolution may not be a single one; in this work, power consumption is taken into consideration, together with the quality of filtering, as the measure of performance, of a noisy image. Pareto optimality is applied to the evolutionary process, in order to find a representative set of optimal solutions as for performance and power consumption. The main contributions of this paper are: implementing an evolvable system on a low-power Spartan-6 FPGA included in a Wireless Sensor Network node and, by enabling the availability of a real measure of power consumption at run-time, achieving the capability of multi-objective evolution, that yields different optimal configurations, among which the selected one will depend on the relative “weights” of performance and power consumption.

Monolithic master oscillator power amplifier at 1.58 µm for lidar measurements

Nowadays the interest in high power semiconductor devices is growing for applications such as telemetry, lidar system or free space communications. Indeed semiconductor devices can be an alternative to solid state lasers because they are more compact and less power consuming. These characteristics are very important for constrained and/or low power supply environment such as airplanes or satellites. Lots of work has been done in the 800-1200 nm range for integrated and free space Master Oscillator Power Amplifier (MOPA) [1]-[3]. At 1.5 ?m, the only commercially available MOPA is from QPC [4]: the fibred output power is about 700 mW and the optical linewidth is 500 kHz. In this paper, we first report on the simulations we have done to determine the appropriate vertical structure and architecture for a good MOPA at 1.58 ?m (section II). Then we describe the fabrication of the devices (section III). Finally we report on the optical and electrical measurements we have done for various devices (section IV).

Towards a real-time 3D object recognition pipeline on mobile GPGPU computing platforms using low-cost RGB-D sensors

In this project, we propose the implementation of a 3D object recognition system which will be optimized to operate under demanding time constraints. The system must be robust so that objects can be recognized properly in poor light conditions and cluttered scenes with significant levels of occlusion. An important requirement must be met: the system must exhibit a reasonable performance running on a low power consumption mobile GPU computing platform (NVIDIA Jetson TK1) so that it can be integrated in mobile robotics systems, ambient intelligence or ambient assisted living applications. The acquisition system is based on the use of color and depth (RGB-D) data streams provided by low-cost 3D sensors like Microsoft Kinect or PrimeSense Carmine. The range of algorithms and applications to be implemented and integrated will be quite broad, ranging from the acquisition, outlier removal or filtering of the input data and the segmentation or characterization of regions of interest in the scene to the very object recognition and pose estimation. Furthermore, in order to validate the proposed system, we will create a 3D object dataset. It will be composed by a set of 3D models, reconstructed from common household objects, as well as a handful of test scenes in which those objects appear. The scenes will be characterized by different levels of occlusion, diverse distances from the elements to the sensor and variations on the pose of the target objects. The creation of this dataset implies the additional development of 3D data acquisition and 3D object reconstruction applications. The resulting system has many possible applications, ranging from mobile robot navigation and semantic scene labeling to human-computer interaction (HCI) systems based on visual information.

A multi-modular second life hybrid battery energy storage system for utility grid applications

The modern grid system or the smart grid is likely to be populated with multiple distributed energy sources, e.g. wind power, PV power, Plug-in Electric Vehicle (PEV). It will also include a variety of linear and nonlinear loads. The intermittent nature of renewable energies like PV, wind turbine and increased penetration of Electric Vehicle (EV) makes the stable operation of utility grid system challenging. In order to ensure a stable operation of the utility grid system and to support smart grid functionalities such as, fault ride-through, frequency response, reactive power support, and mitigation of power quality issues, an energy storage system (ESS) could play an important role. A fast acting bidirectional energy storage system which can rapidly provide and absorb power and/or VARs for a sufficient time is a potentially valuable tool to support this functionality. Battery energy storage systems (BESS) are one of a range suitable energy storage system because it can provide and absorb power for sufficient time as well as able to respond reasonably fast. Conventional BESS already exist on the grid system are made up primarily of new batteries. The cost of these batteries can be high which makes most BESS an expensive solution. In order to assist moving towards a low carbon economy and to reduce battery cost this work aims to research the opportunities for the re-use of batteries after their primary use in low and ultra-low carbon vehicles (EV/HEV) on the electricity grid system. This research aims to develop a new generation of second life battery energy storage systems (SLBESS) which could interface to the low/medium voltage network to provide necessary grid support in a reliable and in cost-effective manner. The reliability/performance of these batteries is not clear, but is almost certainly worse than a new battery. Manufacturers indicate that a mixture of gradual degradation and sudden failure are both possible and failure mechanisms are likely to be related to how hard the batteries were driven inside the vehicle. There are several figures from a number of sources including the DECC (Department of Energy and Climate Control) and Arup and Cenex reports indicate anything from 70,000 to 2.6 million electric and hybrid vehicles on the road by 2020. Once the vehicle battery has degraded to around 70-80% of its capacity it is considered to be at the end of its first life application. This leaves capacity available for a second life at a much cheaper cost than a new BESS Assuming a battery capability of around 5-18kWhr (MHEV 5kWh - BEV 18kWh battery) and approximate 10 year life span, this equates to a projection of battery storage capability available for second life of >1GWhrs by 2025. Moreover, each vehicle manufacturer has different specifications for battery chemistry, number and arrangement of battery cells, capacity, voltage, size etc. To enable research and investment in this area and to maximize the remaining life of these batteries, one of the design challenges is to combine these hybrid batteries into a grid-tie converter where their different performance characteristics, and parameter variation can be catered for and a hot swapping mechanism is available so that as a battery ends it second life, it can be replaced without affecting the overall system operation. This integration of either single types of batteries with vastly different performance capability or a hybrid battery system to a grid-tie 3 energy storage system is different to currently existing work on battery energy storage systems (BESS) which deals with a single type of battery with common characteristics. This thesis addresses and solves the power electronic design challenges in integrating second life hybrid batteries into a grid-tie energy storage unit for the first time. This study details a suitable multi-modular power electronic converter and its various switching strategies which can integrate widely different batteries to a grid-tie inverter irrespective of their characteristics, voltage levels and reliability. The proposed converter provides a high efficiency, enhanced control flexibility and has the capability to operate in different operational modes from the input to output. Designing an appropriate control system for this kind of hybrid battery storage system is also important because of the variation of battery types, differences in characteristics and different levels of degradations. This thesis proposes a generalised distributed power sharing strategy based on weighting function aims to optimally use a set of hybrid batteries according to their relative characteristics while providing the necessary grid support by distributing the power between the batteries. The strategy is adaptive in nature and varies as the individual battery characteristics change in real time as a result of degradation for example. A suitable bidirectional distributed control strategy or a module independent control technique has been developed corresponding to each mode of operation of the proposed modular converter. Stability is an important consideration in control of all power converters and as such this thesis investigates the control stability of the multi-modular converter in detailed. Many controllers use PI/PID based techniques with fixed control parameters. However, this is not found to be suitable from a stability point-of-view. Issues of control stability using this controller type under one of the operating modes has led to the development of an alternative adaptive and nonlinear Lyapunov based control for the modular power converter. Finally, a detailed simulation and experimental validation of the proposed power converter operation, power sharing strategy, proposed control structures and control stability issue have been undertaken using a grid connected laboratory based multi-modular hybrid battery energy storage system prototype. The experimental validation has demonstrated the feasibility of this new energy storage system operation for use in future grid applications.