Quantitative evaluation of three reconfiguration strategies on FPGAs: a case study

Reconfigurable computing is becoming an important new alternative for implementing computations. Field programmable gate arrays (FPGAs) are the ideal integrated circuit technology to experiment with the potential benefits of using different strategies of circuit specialization by reconfiguration. The final form of the reconfiguration strategy is often non-trivial to determine. Consequently, in this paper, we examine strategies for reconfiguration and, based on our experience, propose general guidelines for the tradeoffs using an area-time metric called functional density. Three experiments are set up to explore different reconfiguration strategies for FPGAs applied to a systolic implementation of a scalar quantizer used as a case study. Quantitative results for each experiment are given. The regular nature of the example means that the results can be generalized to a wide class of industry-relevant problems based on arrays.

Modelling human dynamics in-situ for rehabilitation and therapy robots

This paper outlines some rehabilitation applications of manipulators and identifies that new approaches demand that the robot make an intimate contact with the user. Design of new generations of manipulators with programmable compliance along with higher level controllers that can set the compliance appropriately for the task, are both feasible propositions. We must thus gain a greater insight into the way in which a person interacts with a machine, particularly given that the interaction may be non-passive. We are primarily interested in the change in wrist and arm dynamics as the person co-contracts his/her muscles. It is observed that this leads to a change in stiffness that can push an actuated interface into a limit cycle. We use both experimental results gathered from a PHANToM haptic interface and a mathematical model to observe this effect. Results are relevant to the fields of rehabilitation and therapy robots, haptic interfaces, and telerobotics

TCL/TK for EDA tools

Tcl/Tk scripting language has become the de-facto standard for EDA tools. This paper explains how to start working with Tcl/Tk using simple examples. Two complete applications are presented to show in more detail the capabilities of the language. In one script average power consumption of a digital system is automated. A second script creates a virtual display driven by the simulation of a graphic card.

Generic construction of monitors for floating point unit designs

This paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

This paper proposes a parallel hardware architecture for image feature detection based on the Scale Invariant Feature Transform algorithm and applied to the Simultaneous Localization And Mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320 x 240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations oil performance, area and accuracy.

EXPLOITING A GENERIC APPROACH TO CONSTRUCT COMPONENT-BASED SYSTEMS SOFTWARE IN LINUX ENVIRONMENTS

Component-based software engineering has recently emerged as a promising solution to the development of system-level software. Unfortunately, current approaches are limited to specific platforms and domains. This lack of generality is particularly problematic as it prevents knowledge sharing and generally drives development costs up. In the past, we have developed a generic approach to component-based software engineering for system-level software called OpenCom. In this paper, we present OpenComL an instantiation of OpenCom to Linux environments and show how it can be profiled to meet a range of system-level software in Linux environments. For this, we demonstrate its application to constructing a programmable router platform and a middleware for parallel environments.

Electrocombustion of humic acid and removal of algae from aqueous solutions

This paper reports experiments involving the electrochemical combustion of humic acid (HA) and removal of algae from pond water. An electrochemical flow reactor with a boron-doped diamond film anode was used and constant current experiments were conducted in batch recirculation mode. The mass transfer characteristics of the electrochemical device were determined by voltammetric experiments in the potential region of water stability, followed by a controlled current experiment in the potential region of oxygen evolution. The average mass transfer coefficient was 5.2 x 10(-5) m s(-1). The pond water was then processed to remove HA and algae in the conditions in which the reaction combustion occurred under mass transfer control. To this end, the mass transfer coefficient was used to estimate the initial limiting current density applied in the electrolytic experiments. As expected, all the parameters analyzed here-solution absorbance at 270 nm, total phenol concentration and total organic carbon concentration-decayed according to first-order kinetics. Since the diamond film anode successfully incinerated organic matter, the electrochemical system proved to be predictable and programmable.

Mjukvaruverktyg för loggning och analys avindustriella processer

This report discusses developing a software log tool for analysis of industrial processes. The target was to develop software that can help electro Engineers for monitor and fault finding in industrial processes. The tool is called PLS (Process log server), and is developed in Visual Studio.NET Framework 2005. PLS works as a client with Beijer Electronics OPC Server. The program is able to read data from PLC (Programmable Logic Controller), trough the OPC Server. PLS connects to all kind of controllers that is supported by the Beijer Electronics OPC Server. Signal data is stored in a database for later analysis. Chosen signals data can easily be exported into a text file. The text file is adopted for import to MS Office Excel. User manual [UM-07] is written as a separate document. The software acted stable through the function test. The final product becomes a first-rate tool that is simple to use. As an advantage, the software can be developed with more functions in the future.

Energy Analysis within Industrial Hydraulics and Correspondent Solar PV System Design

Energy efficiency and renewable energy use are two main priorities leading to industrial sustainability nowadays according to European Steel Technology Platform (ESTP). Modernization efforts can be done by industries to improve energy consumptions of the production lines. These days, steel making industrial applications are energy and emission intensive. It was estimated that over the past years, energy consumption and corresponding CO2 generation has increased steadily reaching approximately 338.15 parts per million in august 2010 [1]. These kinds of facts and statistics have introduced a lot of room for improvement in energy efficiency for industrial applications through modernization and use of renewable energy sources such as solar Photovoltaic Systems (PV).The purpose of this thesis work is to make a preliminary design and simulation of the solar photovoltaic system which would attempt to cover the energy demand of the initial part of the pickling line hydraulic system at the SSAB steel plant. For this purpose, the energy consumptions of this hydraulic system would be studied and evaluated and a general analysis of the hydraulic and control components performance would be done which would yield a proper set of guidelines contributing towards future energy savings. The results of the energy efficiency analysis showed that the initial part of the pickling line hydraulic system worked with a low efficiency of 3.3%. Results of general analysis showed that hydraulic accumulators of 650 liter size should be used by the initial part pickling line system in combination with a one pump delivery of 100 l/min. Based on this, one PV system can deliver energy to an AC motor-pump set covering 17.6% of total energy and another PV system can supply a DC hydraulic pump substituting 26.7% of the demand. The first system used 290 m2 area of the roof and was sized as 40 kWp, the second used 109 m2 and was sized as 15.2 kWp. It was concluded that the reason for the low efficiency was the oversized design of the system. Incremental modernization efforts could help to improve the hydraulic system energy efficiency and make the design of the solar photovoltaic system realistically possible. Two types of PV systems where analyzed in the thesis work. A method was found calculating the load simulation sequence based on the energy efficiency studies to help in the PV system simulations. Hydraulic accumulators integrated into the pickling line worked as energy storage when being charged by the PV system as well.

Desenvolvimento de arquitetura para sistemas de reconhecimento automático de voz baseados em modelos ocultos de Markov

Este trabalho foi realizado dentro da área de reconhecimento automático de voz (RAV). Atualmente, a maioria dos sistemas de RAV é baseada nos modelos ocultos de Markov (HMMs) [GOM 99] [GOM 99b], quer utilizando-os exclusivamente, quer utilizando-os em conjunto com outras técnicas e constituindo sistemas híbridos. A abordagem estatística dos HMMs tem mostrado ser uma das mais poderosas ferramentas disponíveis para a modelagem acústica e temporal do sinal de voz. A melhora da taxa de reconhecimento exige algoritmos mais complexos [RAV 96]. O aumento do tamanho do vocabulário ou do número de locutores exige um processamento computacional adicional. Certas aplicações, como a verificação de locutor ou o reconhecimento de diálogo podem exigir processamento em tempo real [DOD 85] [MAM 96]. Outras aplicações tais como brinquedos ou máquinas portáveis ainda podem agregar o requisito de portabilidade, e de baixo consumo, além de um sistema fisicamente compacto. Tais necessidades exigem uma solução em hardware. O presente trabalho propõe a implementação de um sistema de RAV utilizando hardware baseado em FPGAs (Field Programmable Gate Arrays) e otimizando os algoritmos que se utilizam no RAV. Foi feito um estudo dos sistemas de RAV e das técnicas que a maioria dos sistemas utiliza em cada etapa que os conforma. Deu-se especial ênfase aos Modelos Ocultos de Markov, seus algoritmos de cálculo de probabilidades, de treinamento e de decodificação de estados, e sua aplicação nos sistemas de RAV. Foi realizado um estudo comparativo dos sistemas em hardware, produzidos por outros centros de pesquisa, identificando algumas das suas características mais relevantes. Foi implementado um modelo de software, descrito neste trabalho, utilizado para validar os algoritmos de RAV e auxiliar na especificação em hardware. Um conjunto de funções digitais implementadas em FPGA, necessárias para o desenvolvimento de sistemas de RAV é descrito. Foram realizadas algumas modificações nos algoritmos de RAV para facilitar a implementação digital dos mesmos. A conexão, entre as funções digitais projetadas, para a implementação de um sistema de reconhecimento de palavras isoladas é aqui apresentado. A implementação em FPGA da etapa de pré-processamento, que inclui a pré-ênfase, janelamento e extração de características, e a implementação da etapa de reconhecimento são apresentadas finalmente neste trabalho.

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Análise de redes em procedimentos de cooperação indireta: utilização no sistema de recomendações da Biblioteca Karl A. Boedecker

Sistemas de recomendação baseados cooperação indireta podem ser implementados em bibliotecas por meio da aplicação de conceitos e procedimentos de análise de redes. Uma medida de distância temática, inicialmente desenvolvida para variáveis dicotômicas, foi generalizada e aplicada a matrizes de co-ocorrências, permitindo o aproveitando de toda a informação disponível sobre o comportamento dos usuários com relação aos itens consultados. Como resultado formaram-se subgrupos especializados altamente coerentes, para os quais listas-base e listas personalizadas foram geradas da maneira usual. Aplicativos programáveis capazes de manipularem matrizes, como o software S-plus, foram utilizados para os cálculos (com vantagens sobre o software especializado UCINET 5.0), sendo suficientes para o processamento de grupos temáticos de até 10.000 usuários.

Uma interface para o aumento da faixa de freqüências de operação de FPAAS

O crescente avanço nas mais diversas áreas da eletrônica, desde instrumentação em baixa freqüência até telecomunicações operando em freqüências muito elevadas, e a necessidade de soluções baratas em curto espaço de tempo que acompanhem a demanda de mercado, torna a procura por circuitos programáveis, tanto digitais como analógicos, um ponto comum em diversas pesquisas. Os dispositivos digitais programáveis, que têm como grande representante os Field Programmable Gate Arrays (FPGAs), vêm apresentando um elevado e contínuo crescimento em termos de complexidade, desempenho e número de transistores integrados, já há várias décadas. O desenvolvimento de dispositivos analógicos programáveis (Field Programmable Analog Arrays – FPAAs), entretanto, esbarra em dois pontos fundamentais que tornam sua evolução um tanto latente: a estreita largura de banda alcançada, conseqüência da necessidade de um grande número de chaves de programação e reconfiguração, e a elevada área consumida por componentes analógicos como resistores e capacitores, quando integrados em processos VLSI Este trabalho apresenta uma proposta para aumentar a faixa de freqüências das aplicações passíveis de serem utilizadas tanto em FPAAs comerciais quanto em outros FPAAs, através da utilização de uma interface de translação e seleção de sinais, mantendo características de programabilidade do FPAA em questão, sem aumentar em muito sua potência consumida. A proposta, a simulação e a implementação da interface são apresentadas ao longo desta dissertação. Resultados de simulação e resultados práticos obtidos comprovam a eficácia da proposta.

Ambiente computacional paradesenvolvimento de aplicações de controladores lógicos programáveis baseado em linguagens SFC e ST

This work proposes an environment for programming programmable logic controllers applied to oil wells with BCP type method of artificially lifting. The environment will have an editor based in the diagram of sequential functions for programming of PLCs. This language was chosen due to the fact of being high-level and accepted by the international standard IEC 61131-3. The use of these control programs in real PLC will be possible with the use of an intermediate level of language based on XML specification PLCopen T6 XML. For the testing and validation of the control programs, an area should be available for viewing variables obtained through communication with a real PLC. Thus, the main contribution of this work is to develop a computational environment that allows: modeling, testing and validating the controls represented in SFC and applied in oil wells with BCP type method of artificially lifting