Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Deposition of c-axis orientation aluminum nitride films on flexible polymer substrates by reactive direct-current magnetron sputtering

Aluminum nitride (AlN) piezoelectric thin films with c-axis crystal orientation on polymer substrates can potentially be used for development of flexible electronics and lab-on-chip systems. In this study, we investigated the effects of deposition parameters on the crystal structure of AlN thin films on polymer substrates deposited by reactive direct-current magnetron sputtering. The results show that low sputtering pressure as well as optimized N 2/Ar flow ratio and sputtering power is beneficial for AlN (002) orientation and can produce a highly (002) oriented columnar structure on polymer substrates. High sputtering power and low N 2/Ar flow ratio increase the deposition rate. In addition, the thickness of Al underlayer also has a strong influence on the film crystallography. The optimal deposition parameters in our experiments are: deposition pressure 0.38 Pa, N 2/Ar flow ratio 2:3, sputtering power 414 W, and thickness of Al underlayer less than 100 nm. © 2012 Elsevier B.V. All rights reserved.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

Sub-nanosecond silicon-on-insulator optical micro-ring switch with low crosstalk

We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator (SOI) dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-mu m-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of < 400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor (CMOS) compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.

Fabrication of triplexers based on flattop SOI AWG

A triplexer is fabricated based on SOI arrayed waveguide gratings (AWGs). Three wavelengths of the triplexer operate at different diffraction orders of an arrayed waveguide grating. The signals of 1490 nm and 1550 nm, which are input from central input waveguide of an AWG, are demultiplexed and the signal of 1310 nm, which is input from central output waveguide of an AWG, is uploaded. The tested results show that the downloaded and uploaded signals have flat-top response. The insertion loss is 9 dB on chip, the nonadjacent crosstalk is less than -30 dB for 1490 nm and 1301 nm, and is less than -25 dB for 1550 nm, the 3 dB bandwidth equates that of the input light source.

The design algorithm of an associative memory neural network

A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.

Potential frequency bandwidth estimation of TO packaging techniques for photodiode modules

Scattering parameters of photodiode chip, TO header and TO packaged module are measured, and the effects of TO packaging network on the high-frequency response of photodiode are investigated. Based on the analysis, the potential bandwidth of TO packaging techniques is estimated from the scattering parameters of the TO packaging network. Another method for estimating the potential bandwidth from the equivalent circuit for the TO packaged photodiode model is also presented. The results obtained using both methods show that the TO packaging techniques used in the experiments can potentially achieve a frequency bandwidth of 22 GHz.

Monolithic optical gates based on integration of evanescently-coupled uni-traveling-carrier photodiodes and electroabsorption modulators

We report on chip-scale optical gates based on the integration of evanescent waveguide unitraveling-carrier photodiodes (EC-UTC-PDs) and intra-step quantum well electroabsorption modulators (IQW-EAMs) on n-InP substrates. These devices exhibit simultaneously 2.1 GHz and -16.2 dB RF-gain at 21 GHz with a 450 Omega thin-film resistor and a bypass capacitor integrated on a chip.

Real-time data processing of interferential imaging spectrometer based on FPGA

Based on the data processing technologies of interferential spectrometer, a sort of real-time data processing system on chip of interferential imaging spectrometer was studied based on large capacitance and high speed field programmable gate array( FPGA) device. The system integrates both interferograrn sampling and spectrum rebuilding on a single chip of FPGA and makes them being accomplished in real-time with advantages such as small cubage, fast speed and high reliability. It establishes a good technical foundation in the applications of imaging spectrometer on target detection and recognition in real-time.

Electrochemical detector based on sol-gel-derived carbon composite material for capillary electrophoresis microchips

An on-chip disk electrode based on sol-gel-derived carbon composite material could be easily and reproducibly fabricated. Unlike other carbon-based electrodes reported previously, this detector is rigid, convenient to fabricate, and amenable to chemical modifications. Based on the stable and reproducible characters of this detector, a copper particle-modified detector was developed for the detection of carbohydrates which extends the application of the carbon-based electrode. In our experiments, the performance of the new integrated detector for rapid on-chip measurement of epinephrine and glucose was illustrated. Experimental procedures including the fabrication of this detector, the configuration of separation channel outlet and electrode verge, and the performance characteristics of this new electrochemical detector were investigated.

Message-Driven Processor Architecture: Verson 11

The Message-Driven Processor is a node of a large-scale multiprocessor being developed by the Concurrent VLSI Architecture Group. It is intended to support fine-grained, message passing, parallel computation. It contains several novel architectural features, such as a low-latency network interface, extensive type-checking hardware, and on-chip memory that can be used as an associative lookup table. This document is a programmer's guide to the MDP. It describes the processor's register architecture, instruction set, and the data types supported by the processor. It also details the MDP's message sending and exception handling facilities.

The M-Machine Multicomputer

The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semiconductor technology and the demands of programming systems. The M- Machine computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 12 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine and describes how its mechanisms maximize both single thread performance and overall system throughput.

An Analog VLSI Chip for Estimating the Focus of Expansion

For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a real-time analog VLSI chip which estimates the focus of expansion (FOE) from measured time-varying images. Our approach assumes a camera moving through a fixed world with translational velocity; the FOE is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the FOE gives the direction of 3-D translation. The algorithm we use for estimating the FOE minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the FOE. This minimization is not straightforward, because the relationship between the brightness derivatives depends on the unknown distance to the surface being imaged. However, image points where brightness is instantaneously constant play a critical role. Ideally, the FOE would be at the intersection of the tangents to the iso-brightness contours at these "stationary" points. In practice, brightness derivatives are hard to estimate accurately given that the image is quite noisy. Reliable results can nevertheless be obtained if the image contains many stationary points and the point is found that minimizes the sum of squares of the perpendicular distances from the tangents at the stationary points. The FOE chip calculates the gradient of this least-squares minimization sum, and the estimation is performed by closing a feedback loop around it. The chip has been implemented using an embedded CCD imager for image acquisition and a row-parallel processing scheme. A 64 x 64 version was fabricated in a 2um CCD/ BiCMOS process through MOSIS with a design goal of 200 mW of on-chip power, a top frame rate of 1000 frames/second, and a basic accuracy of 5%. A complete experimental system which estimates the FOE in real time using real motion and image scenes is demonstrated.

Collaboration on procurement of e-content between the National Health Service and higher education in the UK

Urquhart, C. J., Cox, A. M.& Spink, S. (2007). Collaboration on procurement of e-content between the National Health Service and higher education in the UK. Interlending & Document Supply, 35(3), 164-170. Sponsorship: JISC, LKDN

Electrochemical biosensor based on microfabricated electrode arrays for life sciences applications

In developing a biosensor, the utmost important aspects that need to be emphasized are the specificity and selectivity of the transducer. These two vital prerequisites are of paramount in ensuring a robust and reliable biosensor. Improvements in electrochemical sensors can be achieved by using microelectrodes and to modify the electrode surface (using chemical or biological recognition layers to improve the sensitivity and selectivity). The fabrication and characterisations of silicon-based and glass-based gold microelectrode arrays with various geometries (band and disc) and dimension (ranging from 10 μm-100 nm) were reported. It was found that silicon-based transducers of 10 μm gold microelectrode array exhibited the most stable and reproducible electrochemical measurements hence this dimension was selected for further study. Chemical electrodeposition on both 10 μm microband and microdisc were found viable by electro-assisted self-assembled sol-gel silica film and nanoporous-gold electrodeposition respectively. The fabrication and characterisations of on-chip electrochemical cell was also reported with a fixed diameter/width dimension and interspacing variation. With this regard, the 10 μm microelectrode array with interspacing distance of 100 μm exhibited the best electrochemical response. Surface functionalisations on single chip of planar gold macroelectrodes were also studied for the immobilisation of histidine-tagged protein and antibody. Imaging techniques such as atomic force microscopy, fluorescent microscopy or scanning electron microscope were employed to complement the electrochemical characterisations. The long-chain thiol of self-assembled monolayer with NTA-metal ligand coordination was selected for the histidine-tagged protein while silanisation technique was selected for the antibody immobilisation. The final part of the thesis described the development of a T-2 labelless immunosensor using impedimetric approach. Good antibody calibration curve was obtained for both 10 μm microband and 10 μm microdisc array. For the establishment of the T-2/HT-2 toxin calibration curve, it was found that larger microdisc array dimension was required to produce better calibration curve. The calibration curves established in buffer solution show that the microelectrode arrays were sensitive and able to detect levels of T-2/HT-2 toxin as low as 25 ppb (25 μg kg-1) with a limit of quantitation of 4.89 ppb for a 10 μm microband array and 1.53 ppb for the 40 μm microdisc array.