Digital Elevation Models and GIS for watershed modelling and flood prediction - A case study of Accra Ghana

Geographical Information Systems (GIS) and Digital Elevation Models (DEM) can be used to perform many geospatial and hydrological modelling including drainage and watershed delineation, flood prediction and physical development studies of urban and rural settlements. This paper explores the use of contour data and planimetric features extracted from topographic maps to derive digital elevation models (DEMs) for watershed delineation and flood impact analysis (for emergency preparedness) of part of Accra, Ghana in a GIS environment. In the study two categories of DEMs were developed with 5 m contour and planimetric topographic data; bare earth DEM and built environment DEM. These derived DEMs were used as terrain inputs for performing spatial analysis and obtaining derivative products. The generated DEMs were used to delineate drainage patterns and watershed of the study area using ArcGIS desktop and its ArcHydro extension tool from Environmental Systems Research Institute (ESRI). A vector-based approach was used to derive inundation areas at various flood levels. The DEM of built-up areas was used as inputs for determining properties which will be inundated in a flood event and subsequently generating flood inundation maps. The resulting inundation maps show that about 80% areas which have perennially experienced extensive flooding in the city falls within the predicted flood extent. This approach can therefore provide a simplified means of predicting the extent of inundation during flood events for emergency action especially in less developed economies where sophisticated technologies and expertise are hard to come by. © Springer Science + Business Media B.V. 2009.

80 GSPS photonic analogue to digital conversion system using broadband continuous wave source

An 80 GSPS photonic ADC system is demonstrated, using broadband MLL and dispersive fibre to form a continuous waveform with time-wavelength mapping, and AWG to channelise. Tests are carried out for RF signals up to 10GHz. © 2005 Optical Society of America.

Crosstalk analysis of a fiber laser sensor array system based on digital phase-generated carrier scheme

A detailed study on analyzing the crosstalk in a wavelength division multiplexed fiber laser sensor array system based on a digital phase generated carrier interferometric interrogation scheme is reported. The crosstalk effects induced by the limited optical channel isolation of a dense wavelength division demultiplexer (DWDM) are presented, and the necessary channel isolation to keep the crosstalk negligible to the output signal was calculated via Bessel function expansion and demonstrated by a two serial fiber laser sensors system. Finally, a three-element fiber laser sensor array system with a 50-dB channel-isolation DWDM was built up. Experimental results demonstrated that there was no measurable crosstalk between the output channels.

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

Improved digital processing method used for image motion measurement based on hybrid opto-digital joint transform correlator

Hybrid opto-digital joint transform correlator (HODJTC) is effective for image motion measurement, but it is different from the traditional joint transform correlator because it only has one optical transform and the joint power spectrum is directly input into a digital processing unit to compute the image shift. The local cross-correlation image can be directly obtained by adopting a local Fourier transform operator. After the pixel-level location of cross-correlation peak is initially obtained, the up-sampling technique is introduced to relocate the peak in even higher accuracy. With signal-to-noise ratio >= 20 dB, up-sampling factor k >= 10 and the maximum image shift <= 60 pixels, the root-mean-square error of motion measurement accuracy can be controlled below 0.05 pixels.

Interaction of additive and quantization noises in digital PLLs

Phase-locked loops (PLLs) are a crucial component in modern communications systems. Comprising of a phase-detector, linear filter, and controllable oscillator, they are widely used in radio receivers to retrieve the information content from remote signals. As such, they are capable of signal demodulation, phase and carrier recovery, frequency synthesis, and clock synchronization. Continuous-time PLLs are a mature area of study, and have been covered in the literature since the early classical work by Viterbi [1] in the 1950s. With the rise of computing in recent decades, discrete-time digital PLLs (DPLLs) are a more recent discipline; most of the literature published dates from the 1990s onwards. Gardner [2] is a pioneer in this area. It is our aim in this work to address the difficulties encountered by Gardner [3] in his investigation of the DPLL output phase-jitter where additive noise to the input signal is combined with frequency quantization in the local oscillator. The model we use in our novel analysis of the system is also applicable to another of the cases looked at by Gardner, that is the DPLL with a delay element integrated in the loop. This gives us the opportunity to look at this system in more detail, our analysis providing some unique insights into the variance `dip' seen by Gardner in [3]. We initially provide background on the probability theory and stochastic processes. These branches of mathematics are the basis for the study of noisy analogue and digital PLLs. We give an overview of the classical analogue PLL theory as well as the background on both the digital PLL and circle map, referencing the model proposed by Teplinsky et al. [4, 5]. For our novel work, the case of the combined frequency quantization and noisy input from [3] is investigated first numerically, and then analytically as a Markov chain via its Chapman-Kolmogorov equation. The resulting delay equation for the steady-state jitter distribution is treated using two separate asymptotic analyses to obtain approximate solutions. It is shown how the variance obtained in each case matches well to the numerical results. Other properties of the output jitter, such as the mean, are also investigated. In this way, we arrive at a more complete understanding of the interaction between quantization and input noise in the first order DPLL than is possible using simulation alone. We also do an asymptotic analysis of a particular case of the noisy first-order DPLL with delay, previously investigated by Gardner [3]. We show a unique feature of the simulation results, namely the variance `dip' seen for certain levels of input noise, is explained by this analysis. Finally, we look at the second-order DPLL with additive noise, using numerical simulations to see the effects of low levels of noise on the limit cycles. We show how these effects are similar to those seen in the noise-free loop with non-zero initial conditions.

Chemical and biological applications of digital-microfluidic devices

The advent of digital microfluidic lab-on-a-chip (LoC) technology offers a platform for developing diagnostic applications with the advantages of portability, reduction of the volumes of the sample and reagents, faster analysis times, increased automation, low power consumption, compatibility with mass manufacturing, and high throughput. Moreover, digital microfluidics is being applied in other areas such as airborne chemical detection, DNA sequencing by synthesis, and tissue engineering. In most diagnostic and chemical-detection applications, a key challenge is the preparation of the analyte for presentation to the on-chip detection system. Thus, in diagnostics, raw physiological samples must be introduced onto the chip and then further processed by lysing blood cells and extracting DNA. For massively parallel DNA sequencing, sample preparation can be performed off chip, but the synthesis steps must be performed in a sequential on-chip format by automated control of buffers and nucleotides to extend the read lengths of DNA fragments. In airborne particulate-sampling applications, the sample collection from an air stream must be integrated into the LoC analytical component, which requires a collection droplet to scan an exposed impacted surface after its introduction into a closed analytical section. Finally, in tissue-engineering applications, the challenge for LoC technology is to build high-resolution (less than 10 microns) 3D tissue constructs with embedded cells and growth factors by manipulating and maintaining live cells in the chip platform. This article discusses these applications and their implementation in digital-microfluidic LoC platforms. © 2007 IEEE.

Intelligent Assembly Time Analysis Using a Digital Knowledge-Based Approach

The implementation of effective time analysis methods fast and accurately in the era of digital manufacturing has become a significant challenge for aerospace manufacturers hoping to build and maintain a competitive advantage. This paper proposes a structure oriented, knowledge-based approach for intelligent time analysis of aircraft assembly processes within a digital manufacturing framework. A knowledge system is developed so that the design knowledge can be intelligently retrieved for implementing assembly time analysis automatically. A time estimation method based on MOST, is reviewed and employed. Knowledge capture, transfer and storage within the digital manufacturing environment are extensively discussed. Configured plantypes, GUIs and functional modules are designed and developed for the automated time analysis. An exemplar study using an aircraft panel assembly from a regional jet is also presented. Although the method currently focuses on aircraft assembly, it can also be well utilized in other industry sectors, such as transportation, automobile and shipbuilding. The main contribution of the work is to present a methodology that facilitates the integration of time analysis with design and manufacturing using a digital manufacturing platform solution.

Physical Models of Wind Instruments : A Generalized Excitation Coupled with a Modular Tube Simulation Platform

To develop real-time simulations of wind instruments, digital waveguides filters can be used as an efficient representation of the air column. Many aerophones are shaped as horns which can be approximated using conical sections. Therefore the derivation of conical waveguide filters is of special interest. When these filters are used in combination with a generalized reed excitation, several classes of wind instruments can be simulated. In this paper we present the methods for transforming a continuous description of conical tube segments to a discrete filter representation. The coupling of the reed model with the conical waveguide and a simplified model of the termination at the open end are described in the same way. It turns out that the complete lossless conical waveguide requires only one type of filter.Furthermore, we developed a digital reed excitation model, which is purely based on numerical integration methods, i.e., without the use of a look-up table.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

Instructional Methods For Optimal Learning For An Aerospace Assembly Task: digital animation v pictogram-based instructions

Previous studies on work instruction delivery for complex assembly tasks have shown that the mode and delivery method for the instructions in an engineering context can influence both build time and product quality. The benefits of digital, animated instructional formats when compared to static pictures and text only formats have already been demonstrated. Although pictograms have found applications for relatively straight forward operations and activities, their applicability to relatively complex assembly tasks has yet to be demonstrated. This study compares animated instructions and pictograms for the assembly of an aircraft panel. Based around a series of build experiments, the work records build time as well as the number of media references to measure and compare build efficiency. The number of build errors and the time required to correct them is also recorded. The experiments included five participants completing five builds over five consecutive days for each media type. Results showed that on average the total build time was 13.1% lower for the group using animated instructions. The benefit of animated instructions on build time was most prominent in the first three builds, by build four this benefit had disappeared. There were a similar number of instructional references for the two groups over the five builds but the pictogram users required a lot more references during build 1. There were more errors among the group using pictograms requiring more time for corrections during the build.