A method for determining generators’ shares in loads, line flows and losses

This paper presents a new method for calculating the individual generators’ shares in line flows, line losses and loads. The method is described and illustrated on active power flows, but it can be applied in the same way to reactive power flows. Starting from a power flow solution, the line flow matrix is formed. This matrix is used for identifying node types, tracing the power flow from generators downstream to loads, and to determine generators’ participation factors to lines and loads. Neither exhaustive search nor matrix inversion is required. Hence, the method is claimed to be the least computationally demanding amongst all of the similar methods.

Characteristics of the interfacial capacitance in thin film Ba0.5Sr0.5TiO3 capacitors with SrRuO3 and (La, Sr)CoO3 bottom electrodes

Thin film Ba0.5Sr0.5TiO3 (BST) capacitors of thickness similar to75 nm to similar to1200 nm, with Au top electrodes and SrRuO 3 (SRO) or (La, Sr)CoO3 (LSCO) bottom electrodes were fabricated using Pulsed Laser Deposition. Implementing the "series capacitor model," bulk and interfacial capacitance properties were extracted as a function of temperature and frequency. 'Bulk' properties demonstrated typical ceramic behaviour, displaying little frequency dependence and a permittivity and loss peak at 250 K and 150 K respectively. The interfacial component was found to be relatively temperature and frequency independent for the LSCO/BST capacitors, but for the SRO/BST configuration the interfacial capacitance demonstrated moderate frequency and little temperature dependence below T similar to 300 K but a relatively strong frequency and temperature dependence above T similar to3 00 K. This was attributed to the thermal activation of a space charge component combined with a thermally independent background. The activation energy for the space charge was found to be E-A similar to 0.6 eV suggesting de-trapping of electrons from shallow level traps associated with a thin interfacial layer of oxygen vacancies, parallel to the electrodes.

Progressive loss of ferroelectricity under bipolar pulsed fields and experimental determination of non-switchable polarization in Au/Ba0.5Sr0.5TiO3/SrRuO3 thin-film capacitors

175 nm-thick Ba0.5Sr0.5TiO3 (BST) thin film fabricated by pulsed laser deposition (PLD) technique is found to be a mixture of two distributions of material. We discuss whether these two components are nano-regions of paraelectric and ferroelectric phases, or a bimodal grain-size distribution, or an effect of oxygen vacancy gradient from the electrode interface. The fraction of switchable ferroelectric phase decreases under bipolar pulsed fields, but it recovers after removal of the external fields. The plot of capacitance in decreasing dc voltage (C(Vdown arrow) versus that in increasing dc 61 voltage C(Vup arrow) is a superposition of overlapping of two triangles, in contrast to one well-defined triangle for typical ferroelectric SrBi2Ta2O9 thin films.

Bandwidth limitation of two-port fed and self-phased quadrifilar helix antennas

The bandwidth of a resonant quadrifilar helix antenna (QHA) is shown to be strongly dependent on the design of the feed network. In this paper, we compare the impedance and radiation-pattern performance of two QHAs driven by different feed arrangements. A qualitative explanation for the difference in the behaviour of the antenna is given by observing the amplitude and phase distribution of the current in the helices. (c) 2005 Wiley Periodicals, Inc.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.

Extrinsic parameter extraction and RF modelling of CMOS

An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation. (C) 2003 Elsevier Ltd. All rights reserved.

Comparison of Image Transform-Based Features for Visual Speech Recognition in Clean and Corrupted Videos

We present results of a study into the performance of a variety of different image transform-based feature types for speaker-independent visual speech recognition of isolated digits. This includes the first reported use of features extracted using a discrete curvelet transform. The study will show a comparison of some methods for selecting features of each feature type and show the relative benefits of both static and dynamic visual features. The performance of the features will be tested on both clean video data and also video data corrupted in a variety of ways to assess each feature type's robustness to potential real-world conditions. One of the test conditions involves a novel form of video corruption we call jitter which simulates camera and/or head movement during recording.