Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Using Level Sets as the basis for a scalable, parallel geometry engine and mesh generation system

The background to this review paper is research we have performed over recent years aimed at developing a simulation system capable of handling large scale, real world applications implemented in an end-to-end parallel, scalable manner. The particular focus of this paper is the use of a Level Set solid modeling geometry kernel within this parallel framework to enable automated design optimization without topological restrictions and on geometries of arbitrary complexity. Also described is another interesting application of Level Sets: their use in guiding the export of a body-conformal mesh from our basic cut-Cartesian background octree - mesh - this permits third party flow solvers to be deployed. As a practical demonstrations meshes of guaranteed quality are generated and flow-solved for a B747 in full landing configuration and an automated optimization is performed on a cooled turbine tip geometry. Copyright © 2009 by W.N.Dawes.

Tests for conceptual design of 6.6 kV class superconducting fault current limiter with YBCO thin film elements

A superconducting fault current limiter (SFCL) for 6.6 kV and 400 A installed in a cubicle for a distribution network substation was conceptually designed. The SFCL consists of parallel- and series-connected superconducting YBCO elements and a limiting resistor. Before designing the SFCL, some tests were carried out. The width and length of each element used in the tests are 30 mm and 210 mm, respectively. The element consists of YBCO thin film of about 200 nm in thickness on cerium dioxide (CeO2) as a cap-layer on a sapphire substrate by metal-organic deposition with a protective metal coat. In the tests, characteristics of each element, such as over-current, withstand-voltage, and so on, were obtained. From these characteristics, series and parallel connections of the elements, called units, were considered. The characteristics of the units were obtained by tests. From the test results, a single phase prototype SFCL was manufactured and tested. Thus, an SFCL rated at 6.6 kV and 400 A can be designed. © 2009 IEEE.

Using mesoscopic models to design strong and tough biomimetic polymer networks

Using computational modeling, we investigate the mechanical properties of polymeric materials composed of coiled chains, or "globules", which encompass a folded secondary structure and are cross-linked by labile bonds to form a macroscopic network. In the presence of an applied force, the globules can unfold into linear chains and thereby dissipate energy as the network is deformed; the latter attribute can contribute to the toughness of the material. Our goal is to determine how to tailor the labile intra- and intermolecular bonds within the network to produce material exhibiting both toughness and strength. Herein, we use the lattice spring model (LSM) to simulate the globules and the cross-linked network. We also utilize our modified Hierarchical Bell model (MHBM) to simulate the rupture and reforming of N parallel bonds. By applying a tensile deformation, we demonstrate that the mechanical properties of the system are sensitive to the values of N in and N out, the respective values of N for the intra- and intermolecular bonds. We find that the strength of the material is mainly controlled by the value of N out, with the higher value of N out providing a stronger material. We also find that, if N in is smaller than N out, the globules can unfold under the tensile load before the sample fractures and, in this manner, can increase the ductility of the sample. Our results provide effective strategies for exploiting relatively weak, labile interactions (e.g., hydrogen bonding or the thiol/disulfide exchange reaction) in both the intra- and intermolecular bonds to tailor the macroscopic performance of the materials. © 2011 American Chemical Society.

Multi-objective optimisation of horizontal axis wind turbine structure and energy production using aerofoil and blade properties as design variables

The design of wind turbine blades is a true multi-objective engineering task. The aerodynamic effectiveness of the turbine needs to be balanced with the system loads introduced by the rotor. Moreover the problem is not dependent on a single geometric property, but besides other parameters on a combination of aerofoil family and various blade functions. The aim of this paper is therefore to present a tool which can help designers to get a deeper insight into the complexity of the design space and to find a blade design which is likely to have a low cost of energy. For the research we use a Computational Blade Optimisation and Load Deflation Tool (CoBOLDT) to investigate the three extreme point designs obtained from a multi-objective optimisation of turbine thrust, annual energy production as well as mass for a horizontal axis wind turbine blade. The optimisation algorithm utilised is based on Multi-Objective Tabu Search which constitutes the core of CoBOLDT. The methodology is capable to parametrise the spanning aerofoils with two-dimensional Free Form Deformation and blade functions with two tangentially connected cubic splines. After geometry generation we use a panel code to create aerofoil polars and a stationary Blade Element Momentum code to evaluate turbine performance. Finally, the obtained loads are fed into a structural layout module to estimate the mass and stiffness of the current blade by means of a fully stressed design. For the presented test case we chose post optimisation analysis with parallel coordinates to reveal geometrical features of the extreme point designs and to select a compromise design from the Pareto set. The research revealed that a blade with a feasible laminate layout can be obtained, that can increase the energy capture and lower steady state systems loads. The reduced aerofoil camber and an increased L/. D-ratio could be identified as the main drivers. This statement could not be made with other tools of the research community before. © 2013 Elsevier Ltd.

Design trade-offs for energy regeneration and control in vehicle suspensions

This paper investigates the fundamental trade-offs involved in designing energy-regenerative suspensions, in particular, focusing on efficiency of power extraction and its effect on vehicle dynamics and control. It is shown that typical regenerative devices making use of linear-to-rotational elements can be modelled as a parallel arrangement of an inerter and a dissipative admittance. Taking account of typical adjustable parameters of the generator, it is shown, for a given suspension damping coefficient, that the power efficiency ratio scales with inertance. For a typical passenger vehicle, it is shown that there is a feasible compromise, namely that good efficiency is achievable with an inertance value that is not detrimental to vehicle performance. A prototype is designed and tested with a resistive termination and experimental results show good agreement between ideal and experimental admittances. The possibility to use dynamic (rather than purely resistive) loads to improve vehicle control without limiting the energy recovery is discussed. © 2013 Copyright Taylor and Francis Group, LLC.

Design and modelling of a fluid inerter

Mechanical spring-damper network performance can often be improved by the inclusion of a third passive component called the inerter. This ideally has the characteristic that the force at the terminals is directly proportional to the relative acceleration between them. The fluid inerter presented here has advantages over mechanical ball screw devices in terms of simplicity of design. Furthermore, it can be readily adapted to implement various passive network layouts. Variable orifices and valves can be included to provide series or parallel damping. Test data from prototypes with helical tubes have been compared with models to investigate parasitic damping effects of the fluid. © 2013 Copyright Taylor and Francis Group, LLC.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

A High Speed, 12-Channel Parallel, Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8～1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

High Speed VCSEL-Based Parallel Optical Transmission Modules

Design and fabrication of a parallel optical transmitter are reported. The optimized 12 channel parallel optical transmitter,with each channel＇s data rate up to 3Gbit/s,is designed, assembled, and measured. A top-emitting 850nm vertical cavity surface emitting laser（VCSEL） array is adopted as the light source,and the VCSEL chip is directly wire bonded to a 12 channel driver IC. The outputs of the VCSEL array are directly butt coupled into a 12 channel fiber array. Small form factor pluggable （SFP） packaging technology is used in the module to support hot pluggable in application. The performance results of the module are demonstrated. At an operating current of 8mA, an eye diagram at 3Gbit/s is achieved with an optical output of more than 1mW.

Design and numerical analysis for low birefringence silica on silicon waveguides

A new fabrication technology for three-dimensionally buried silica on silicon optical waveguide based on deep etching and thermal oxidation is presented. Using this method, a silicon layer is left at the side of waveguide. The stress distribution and effective refractive index are calculated by using finite element method and finite different beam propagation method, respectively. The results indicate that the stress of silica on silicon optical waveguide fabricated by this method can be matched in parallel and vertical directions and stress birefringence can be effectively reduced due to the side-silicon layer.

Polarization-Insensitive Silica on Silicon Arrayed Waveguide Grating Design

A new technology for fabrication of silica on silicon arrayed waveguide grating (AWG) based on deep etching and thermal oxidation is presented.Using this method,a silicon layer is remained at the side of waveguide.The stress distribution and effective refractive index of waveguide fabricated by this approach are calculated using finite element and finite difference beam propagation method,respectively.The results of these studies indicate that the stress of silica on silicon optical waveguide can be matched in parallel and vertical direction and AWG polarization dependent wavelength (PDλ) can be reduced effectively due to side-silicon layer.

An unusual 3D polycatenane motif generated by the 2D -> 2D parallel -> 3D parallel interpenetration of (4,4) sheets

A fascinating 3D polycatenane-like metal-organic framework with two kinds of helical chains was reported, in which the helical chains exhibit multiple interweaving modes based on the unusual 2D -> 2D parallel -> 3D parallel interpenetration.

A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor

This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.