Analysis of the lateral diffuse metal-oxide semiconductor (LDMOS) power amplifier for cellular base stations

The primary purpose of this thesis was to present a theoretical large-signal analysis to study the power gain and efficiency of a microwave power amplifier for LS-band communications using software simulation. Power gain, efficiency, reliability, and stability are important characteristics in the power amplifier design process. These characteristics affect advance wireless systems, which require low-cost device amplification without sacrificing system performance. Large-signal modeling and input and output matching components are used for this thesis. Motorola's Electro Thermal LDMOS model is a new transistor model that includes self-heating affects and is capable of small-large signal simulations. It allows for most of the design considerations to be on stability, power gain, bandwidth, and DC requirements. The matching technique allows for the gain to be maximized at a specific target frequency. Calculations and simulations for the microwave power amplifier design were performed using Matlab and Microwave Office respectively. Microwave Office is the simulation software used in this thesis. The study demonstrated that Motorola's Electro Thermal LDMOS transistor in microwave power amplifier design process is a viable solution for common-source amplifier applications in high power base stations. The MET-LDMOS met the stability requirements for the specified frequency range without a stability-improvement model. The power gain of the amplifier circuit was improved through proper microwave matching design using input/output-matching techniques. The gain and efficiency of the amplifier improve approximately 4dB and 7.27% respectively. The gain value is roughly .89 dB higher than the maximum gain specified by the MRF21010 data sheet specifications. This work can lead to efficient modeling and development of high power LDMOS transistor implementations in commercial and industry applications.

Georeferenced standardized apparent wave power along the coastline of Cabrera National Park for analysis of essential habitats of littoral species

Wind- induced exposure is one of the major forces shaping the geomorphology and biota in coastal areas. The effect of wave exposure on littoral biota is well known in marine environments (Ekebon et al., 2003; Burrows et al., 2008). In the Cabrera Archipelago National Park wave exposure has demostrated to have an effect on the spatial distribution of different stages of E.marginatus (Alvarez et al., 2010). Standarized average wave exposures during 2008 along the Cabrera Archipelago National park coast line were calculated to be applied in studies of littoral species distribution within the archipelago. Average wave exposure (or apparent wave power) was calculated for points located 50 m equidistant on the coastline following the EXA methodology (EXposure estimates for fragmented Archipelagos) (Ekebon et al., 2003). The average wave exposures were standardized from 1 to 100 (minimum and maximum in the area), showing coastal areas with different levels of mea wave exposure during the year. Input wind data (direction and intensity) from 2008 was registered at the Cabrera mooring located north of Cabrera Archipelago. Data were provided by IMEDEA (CSIC-UIB, TMMOS http://www.imedea.uib-csic.es/tmoos/boyas/). This cartography has been developed under the framework of the project EPIMHAR, funded by the National Park's Network (Spanish Ministry of Environment, Maritime and Rural Affairs, reference: 012/2007 ). Part of this work has been developed under the research programs funded by "Fons de Garantia Agrària i Pesquera de les Illes Balears (FOGAIBA)".

Short-term wind power forecast based on cluster analysis and artificial neural networks

[EN]In this paper an architecture for an estimator of short-term wind farm power is proposed. The estimator is made up of a Linear Machine classifier and a set of k Multilayer Perceptrons, training each one for a specific subspace of the input space. The splitting of the input dataset into the k clusters is done using a k-means technique, obtaining the equivalent Linear Machine classifier from the cluster centroids...

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Voltage and current spectra for matrix power converters

Matrix power converters are used for transforming one alternating-current power supply to another, with different peak voltage and frequency. There are three input lines, with sinusoidally varying voltages which are 120◦ out of phase one from another, and the output is to be delivered as a similar three-phase supply. The matrix converter switches rapidly, to connect each output line in sequence to each of the input lines in an attempt to synthesize the prescribed output voltages. The switching is carried out at high frequency and it is of practical importance to know the frequency spectra of the output voltages and of the input and output currents. We determine in this paper these spectra using a new method, which has significant advantages over the prior default method (a multiple Fourier series technique), leading to a considerably more direct calculation. In particular, the determination of the input current spectrum is feasible here, whereas it would be a significantly more daunting procedure using the prior method instead.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.

Design and characterization of wideband Hall current sensors in BCD technology for smart power and metering applications

Power electronic circuits are moving towards higher switching frequencies, exploiting the capabilities of novel devices to shrink the dimension of passive components. This trend demands sensors capable enough to operate at such high frequencies. This thesis aims to demonstrate through experimental characterization, the broadband capability of a fully integrated CMOS X-Hall current sensor in current mode interfaced with a transimpedance amplifier (TIA), chip CH09, realized in CMOS technology for power electronics applications such as power converters. The system exploits a common-mode control system to operate the dual supply system, 5-V for the X-Hall probe and 1.2-V for the readout. The developed prototype achieves a maximum acquisition bandwidth of 12 MHz, a power consumption of 11.46 mW, resolution of 39 mArms, a sensitivity of 8 % /T, and a FoM of 569-MHz/A2mW, significantly higher than current state-of-the-art. Further enhancements were proposed to CH09 as a new chip CH100, aiming for accuracy levels prerequisite for a real-time power electronic application. The TIA was optimized for a wider bandwidth of 26.7 MHz with nearly 30% reduction of the integrated input referred noise of 26.69 nArms at the probe-AFE interface in the frequency band of DC-30 MHz, and a 10% improvement in the dynamic range. The expected input range is 5-A. The chip incorporates a dual sensing chain for differential sensing to overcome common mode interferences. A novel offset cancellation technique is proposed that would require switching of polarity of bias currents. Thermal gain drift was improved by a factor of 8 and will be digitally calibrated utilizing a new built-in temperature sensor with a post calibration measurement accuracy greater than 1%. The estimated power consumption of the entire system is 55.6 mW. Both prototypes have been implemented through a 90-nm microelectronic process from STMicroelectronics and occupy a silicon area of 2.4 mm2.

Analysis and improvements of four-wire power converters for electric vehicle chargers

A robust and well-distributed backbone charging network is the priority to ensure widespread electrification of road transport, providing a driving experience similar to that of internal combustion engine vehicles. International standards set multiple technical targets for on-board and off-board electric vehicle chargers; output voltage levels, harmonic emissions, and isolation requirements strongly influence the design of power converters. Additionally, smart-grid services such as vehicle-to-grid and vehicle-to-vehicle require the implementation of bi-directional stages that inevitably increase system complexity and component count. To face these design challenges, the present thesis provides a rigorous analysis of four-leg and split-capacitor three-phase four-wire active front-end topologies focusing on the harmonic description under different modulation techniques and conditions. The resulting analytical formulation paves the way for converter performance improvements while maintaining regulatory constraints and technical requirements under control. Specifically, split-capacitor inverter current ripple was characterized as providing closed-form formulations valid for every sub-case ranging from synchronous to interleaved PWM. Outcomes are the base for a novel variable switching PWM technique capable of mediating harmonic content limitation and switching loss reduction. A similar analysis is proposed for four-leg inverters with a broad range of continuous and discontinuous PWM modulations. The general superiority of discontinuous PWM modulation in reducing switching losses and limiting harmonic emission was demonstrated. Developments are realized through a parametric description of the neutral wire inductor. Finally, a novel class of integrated isolated converter topologies is proposed aiming at the neutral wire delivery without employing extra switching components rather than the one already available in typical three-phase inverter and dual-active-bridge back-to-back configurations. The fourth leg was integrated inside the dual-active-bridge input bridge providing relevant component count savings. A novel modified single-phase-shift modulation technique was developed to ensure a seamless transition between working conditions like voltage level and power factor. Several simulations and experiments validate the outcomes.

Analysis and design considerations of resonator arrays for inductive power transfer systems

In the frame of inductive power transfer (IPT) systems, arrays of magnetically coupled resonators have received increasing attention as they are cheap and versatile due to their simple structure. They consist of magnetically coupled coils, which resonate with their self-capacitance or lumped capacitive networks. Of great industrial interest are planar resonator arrays used to power a receiver that can be placed at any position above the array. A thorough circuit analysis has been carried out, first starting from traditional two-coil IPT devices. Then, resonator arrays have been introduced, with particular attention to the case of arrays with a receiver. To evaluate the system performance, a circuit model based on original analytical formulas has been developed and experimentally validated. The results of the analysis also led to the definition of a new doubly-fed array configuration with a receiver that can be placed above it at any position. A suitable control strategy aimed at maximising the transmitted power and the efficiency has been also proposed. The study of the array currents has been carried out resorting to the theory of magneto-inductive waves, allowing useful insight to be highlighted. The analysis has been completed with a numerical and experimental study on the magnetic field distribution originating from the array. Furthermore, an application of the resonator array as a position sensor has been investigated. The position of the receiver is estimated through the measurement of the array input impedance, for which an original analytical expression has been also obtained. The application of this sensing technique in an automotive dynamic IPT system has been discussed. The thesis concludes with an evaluation of the possible applications of two-dimensional resonator arrays in IPT systems. These devices can be used to improve system efficiency and transmitted power, as well as for magnetic field shielding.

Comparação entre métodos para mensuração da potência aeróbia em atletas tetraplégicos= : Comparison of methods for aerobic power assessment in athletes with tetraplegia

Universidade Estadual de Campinas . Faculdade de Educação Física

A concepção estratégico-tática no handebol : implicações para a formação de jogadores inteligentes

Universidade Estadual de Campinas . Faculdade de Educação Física

Reliability and discriminatory power of methods for dental plaque quantification

OBJECTIVE: This in situ study evaluated the discriminatory power and reliability of methods of dental plaque quantification and the relationship between visual indices (VI) and fluorescence camera (FC) to detect plaque. MATERIAL AND METHODS: Six volunteers used palatal appliances with six bovine enamel blocks presenting different stages of plaque accumulation. The presence of plaque with and without disclosing was assessed using VI. Images were obtained with FC and digital camera in both conditions. The area covered by plaque was assessed. Examinations were done by two independent examiners. Data were analyzed by Kruskal-Wallis and Kappa tests to compare different conditions of samples and to assess the inter-examiner reproducibility. RESULTS: Some methods presented adequate reproducibility. The Turesky index and the assessment of area covered by disclosed plaque in the FC images presented the highest discriminatory powers. CONCLUSION: The Turesky index and images with FC with disclosing present good reliability and discriminatory power in quantifying dental plaque.

Power Secant Method applied to natural frequency extraction of Timoshenko beam structures

This work deals with an improved plane frame formulation whose exact dynamic stiffness matrix (DSM) presents, uniquely, null determinant for the natural frequencies. In comparison with the classical DSM, the formulation herein presented has some major advantages: local mode shapes are preserved in the formulation so that, for any positive frequency, the DSM will never be ill-conditioned; in the absence of poles, it is possible to employ the secant method in order to have a more computationally efficient eigenvalue extraction procedure. Applying the procedure to the more general case of Timoshenko beams, we introduce a new technique, named ""power deflation"", that makes the secant method suitable for the transcendental nonlinear eigenvalue problems based on the improved DSM. In order to avoid overflow occurrences that can hinder the secant method iterations, limiting frequencies are formulated, with scaling also applied to the eigenvalue problem. Comparisons with results available in the literature demonstrate the strength of the proposed method. Computational efficiency is compared with solutions obtained both by FEM and by the Wittrick-Williams algorithm.

Living Our Lives on the Edge: Power, Space and Sexual Orientation in Cape Town Townships, South Africa

Much of social science literature about South African cities fails to represent its complex spectrum of sexual practices and associated identities. The unintended effects of such representations are that a compulsory heterosexuality is naturalised in, and reiterative with, dominant constructions of blackness in townships. In this paper, we argue that the assertion of discreet lesbian and gay identities in black townships of a South African city such as Cape Town is influenced by the historical racial and socio-economic divides that have marked urban landscape. In their efforts to recoup a positive sense of gendered personhood, residents have constructed a moral economy anchored in reproductive heterosexuality. We draw upon ethnographic data to show how sexual minorities live their lives vicariously in spaces they have prised open within the extant sex/gender binary. They are able to assert the identities of moffie and man-vrou (mannish woman) without threatening the dominant ideology of heterosexuality.

A high voltage pulse power supply for metal plasma immersion ion implantation and deposition

We describe the design and implementation of a high voltage pulse power supply (pulser) that supports the operation of a repetitively pulsed filtered vacuum arc plasma deposition facility in plasma immersion ion implantation and deposition (Mepiiid) mode. Negative pulses (micropulses) of up to 20 kV in magnitude and 20 A peak current are provided in gated pulse packets (macropulses) over a broad range of possible pulse width and duty cycle. Application of the system consisting of filtered vacuum arc and high voltage pulser is demonstrated by forming diamond-like carbon (DLC) thin films with and without substrate bias provided by the pulser. Significantly enhanced film/substrate adhesion is observed when the pulser is used to induce interface mixing between the DLC film and the underlying Si substrate. (C) 2010 American Institute of Physics. [doi:10.1063/1.3518969]