Projecto de um regulador linear de tensão: LDO

Os reguladores de tensão LDO são utilizados intensivamente na actual indústria de electrónica, são uma parte essencial de um bloco de gestão de potência para um SoC. O aumento de produtos portáteis alimentados por baterias levou ao crescimento de soluções totalmente integradas, o que degrada o rendimento dos blocos analógicos que o constituem face às perturbações introduzidas na alimentação. Desta forma, surge a necessidade de procurar soluções cada vez mais optimizadas, impondo assim novas soluções, e/ou melhoramentos dos circuitos de gestão de potência, tendo como objectivo final o aumento do desempenho e da autonomia dos dispositivos electrónicos. Normalmente este tipo de reguladores tem a corrente de saída limitada, devido a problemas de estabilidade associados. Numa tentativa de evitar a instabilidade para as correntes de carga definidas e aumentar o PSRR do mesmo, é apresentado um método de implementação que tem como objectivo melhorar estas características, em que se pretende aumentar o rendimento e melhorar a resposta à variação da carga. No entanto, a técnica apresentada utiliza polarização adaptativa do estágio de potência, o que implica um aumento da corrente de consumo. O regulador LDO foi implementado na tecnologia CMOS UMC 0.18μm e ocupa uma área inferior a 0,2mm2. Os resultados da simulação mostram que o mesmo suporta uma transição de corrente 10μA para 100mA, com uma queda de tensão entre a tensão de alimentação e a tensão de saída inferior a 200mV. A estabilidade é assegurada para todas as correntes de carga. O tempo de estabelecimento é inferior a 6μs e as variações da tensão de saída relativamente a seu valor nominal são inferiores a 5mV. A corrente de consumo varia entre os 140μA até 200μA, o que permite atingir as especificações proposta para um PSRR de 40dB@10kHz.

Solid-State Bipolar Marx Converter with Output Transformer and Energy Recovery

The purpose of this paper is to present and discuss a general HV topology of the solid-state Marx modulator, for unipolar or bipolar generation connected with a step-up transformer to increase the output voltage applied to a resistive load. Due to the use of an output transformer, discussion about the reset of the transformer is made to guarantee zero average voltage applied to the primary. It is also discussed the transformer magnetizing energy recovering back to the energy storage capacitors. Simulation results for a circuit that generates 100 kV pulses using 1000 V semiconductors are presented and discussed regarding the voltage and current stress on the semiconductors and result obtained.

HVDC transmission systems: Bipolar back-to-back diode clamped multilevel converter with fastoptimum-predictive control and capacitor balancing strategy

Voltage source multilevel power converter structures are being considered for high power high voltage applications where they have well known advantages. Recently, full back-to-back connected multilevel neutral diode clamped converters (NPC) have been used in high voltage direct current (HVDC) transmission systems. Bipolar back-to-back connection of NPCs have advantages in long distance HVDC transmission systems, but highly increased difficulties to balance the dc capacitor voltage dividers on both sending and receiving end NPCs. This paper proposes a fast optimum-predictive controller to balance the dc capacitor voltages and to control the power flow in a long distance HVDCsystem using bipolar back-to-back connected NPCs. For both converter sides, the control strategy considers active and reactive power to establish ac grid currents on sending and receiving ends, while guaranteeing the balancing of both NPC dc bus capacitor voltages. Furthermore, the fast predictivecontroller minimizes the semiconductor switching frequency to reduce global switching losses. The performance and robustness of the new fast predictive control strategy and the associated dc capacitors voltage balancing are evaluated. (C) 2011 Elsevier B.V. All rights reserved.

A Voltage Limiter Circuit for Indoor Light Energy Harvesting Applications

A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

Start-up circuit for low-power indoor light energy harvesting applications

A start-up circuit, used in a micro-power indoor light energy harvesting system, is described. This start-up circuit achieves two goals: first, to produce a reset signal, power-on-reset (POR), for the energy harvesting system, and secondly, to temporarily shunt the output of the photovoltaic (PV) cells, to the output node of the system, which is connected to a capacitor. This capacitor is charged to a suitable value, so that a voltage step-up converter starts operating, thus increasing the output voltage to a larger value than the one provided by the PV cells. A prototype of the circuit was manufactured in a 130 nm CMOS technology, occupying an area of only 0.019 mm(2). Experimental results demonstrate the correct operation of the circuit, being able to correctly start-up the system, even when having an input as low as 390 mV using, in this case, an estimated energy of only 5.3 pJ to produce the start-up.

Enhanced Race-to-halt: a leakage-aware energy management approach for dynamic priority systems

With progressing CMOS technology miniaturization, the leakage power consumption starts to dominate the dynamic power consumption. The recent technology trends have equipped the modern embedded processors with the several sleep states and reduced their overhead (energy/time) of the sleep transition. The dynamic voltage frequency scaling (DVFS) potential to save energy is diminishing due to efficient (low overhead) sleep states and increased static (leakage) power consumption. The state-of-the-art research on static power reduction at system level is based on assumptions that cannot easily be integrated into practical systems. We propose a novel enhanced race-to-halt approach (ERTH) to reduce the overall system energy consumption. The exhaustive simulations demonstrate the effectiveness of our approach showing an improvement of up to 8 % over an existing work.

Fifth harmonic and sag impact on PMSG wind turbines with a balancing new strategy for capacitor voltages

This paper deals with the computing simulation of the impact on permanent magnet synchronous generator wind turbines due to fifth harmonic content and grid voltage decrease. Power converter topologies considered in the simulations are the two-level and the three-level ones. The three-level converters are limited by unbalance voltages in the DC-link capacitors. In order to lessen this limitation, a new control strategy for the selection of the output voltage vectors is proposed. Controller strategies considered in the simulation are respectively based on proportional integral and fractional-order controllers. Finally, a comparison between the results of the simulations with the two controller strategies is presented in order to show the main advantage of the proposed strategy. (C) 2014 Elsevier Ltd. All rights reserved.

Multilevel high-voltage pulse generation based on a new modular solid-state switch

This paper describes a modular solid-state switching cell derived from the Marx generator concept to be used in topologies for generating multilevel unipolar and bipolar high-voltage (HV) pulses into resistive loads. The switching modular cell comprises two ON/OFF semiconductors, a diode, and a capacitor. This cell can be stacked, being the capacitors charged in series and their voltages balanced in parallel. To balance each capacitor voltage without needing any parameter measurement, a vector decision diode algorithm is used in each cell to drive the two switches. Simulation and experimental results, for generating multilevel unipolar and bipolar HV pulses into resistive loads are presented.

A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA

Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores

A MOSFET-only wideband LNA exploiting thermal noise canceling and gain optimization

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Compensação da energia reactiva com minimização de perturbações sobre a rede eléctrica

Trabalho Final de Mestrado para a obtenção de grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Projecto e realização de sensores de temperatura analógicos e digitais

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do Grau de Mestre em Engenharia Electrotécnica e Computadores