Recent progress in high-bit-rate applications of four-wave-mixing in SOAs

Non-linearities in semiconductor optical amplifiers have been used to demonstrate a wide range of functions applicable to future optical networks such as wavelength conversion and optical switching. Four-wave-mixing effects in SOAs have been studied extensively in many laboratories with respect to the underlying physical processes and system applications. At BT Labs an optimisation of SOAs for FWM has been achieved by altering the device active layer composition and by increasing the device length. We will review recent progress at BT Labs in dispersion compensation, wavelength conversion and demultiplexing at bit-rates of 40Gbit/s using these devices.

Mismatched shaping schemes for bit-interleaved coded modulation

We consider bit-interleaved coded modulation (BICM) schemes where, instead of the true bit or symbol probabilities and the constellation used at the transmitter, the decoder uses arbitrary probabilities or reference constellations. We study the corresponding low- and high- signal-to-noise-ratio regimes and show that even in the presence of this extra sources of mismatch, BICM has a negligible penalty with respect to coded modulation. © 2012 IEEE.

Coexistence of high-bit-rate quantum key distribution and data on optical fiber

Quantum key distribution (QKD) uniquely allows distribution of cryptographic keys with security verified by quantum mechanical limits. Both protocol execution and subsequent applications require the assistance of classical data communication channels. While using separate fibers is one option, it is economically more viable if data and quantum signals are simultaneously transmitted through a single fiber. However, noise-photon contamination arising from the intense data signal has severely restricted both the QKD distances and secure key rates. Here, we exploit a novel temporal-filtering effect for noise-photon rejection. This allows high-bit-rate QKD over fibers up to 90 km in length and populated with error-free bidirectional Gb/s data communications. With high-bit rate and range sufficient for important information infrastructures, such as smart cities and 10 Gbit Ethernet, QKD is a significant step closer towards wide-scale deployment in fiber networks.

High bit rate quantum key distribution with 100 dB security

We report the operation of a gigahertz clocked quantum key distribution system featuring high composable and quantifiable security while maintaining more than 1 Mbit/s secure key rate over a 50 km quantum channel. © OSA 2013.

Improved exponents and rates for bit-interleaved coded modulation

Mismatched decoding theory is applied to study the error exponents (both random-coding and expurgated) and achievable rates for bit-interleaved coded modulation (BICM). The gains achieved by constant-composition codes with respect to the the usual random codes are highlighted. © 2013 IEEE.

Room temperature single-photon detectors for high bit rate quantum key distribution

We report room temperature operation of telecom wavelength single-photon detectors for high bit rate quantum key distribution (QKD). Room temperature operation is achieved using InGaAs avalanche photodiodes integrated with electronics based on the self-differencing technique that increases avalanche discrimination sensitivity. Despite using room temperature detectors, we demonstrate QKD with record secure bit rates over a range of fiber lengths (e.g., 1.26 Mbit/s over 50 km). Furthermore, our results indicate that operating the detectors at room temperature increases the secure bit rate for short distances. © 2014 AIP Publishing LLC.

Symmetrical 2-D hermite-gaussian square launch for high bit rate transmission in multimode fiber links

A 2-D Hermite-Gaussian square launch is demonstrated to show improved systems capacity over multimode fiber links. It shows a bandwidth improvement over both center and offset launches and exhibits ±5 ìm misalignment tolerance. © OSA/OFC/NFOEC 2011.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Highly coherent solid-state quantum bit from a pair of quantum dots

In this letter, we propose a scheme to buildup a highly coherent solid-state quantum bit (qubit) from two coupled quantum dots. Quantum information is stored in the state of the electron-hole pair with the electron and hole located in different dots, and universal quantum gates involving any pair of qubits are realized by effective coupling interaction via virtually exchanging cavity photons. (C) 2002 American Institute of Physics.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.