THE OXIDATION-KINETICS OF THIN POLYCRYSTALLINE SILICON FILMS

The oxidation dynamics and morphology of undoped and heavily phosphorus-doped polycrystalline silicon films oxidized at a wide temperature and time range in dry and wet O2 atmosphere have been investigated. It is shown that the oxidation rates of polycrystalline silicon films are different from that of single-crystal silicon when the oxidation temperature is below 1000-degrees-C. There is a characteristic oxidation time, t(c), under which the undoped polysilicon oxide is not only thicker than that of (100)-oriented single-crystal silicon, but also thicker than that of (111)-oriented single-crystal silicon. For phosphorus-doped polycrystalline silicon films, the oxide thickness is thinner not only than that of (111)-oriented, single-crystal silicon, but also thinner than that of (100)-oriented, single-crystal silicon. According to TEM cross-sectional studies, these characteristics are due to the enhanced oxidation at grain boundaries of polycrystalline silicon films. A stress-enhanced oxidation model has been proposed and used to explain successfully the enhanced oxidation at grain boundaries of polycrystalline silicon films. Using this model, the oxidation linear rate constant of polysilicon (B/A)poly has been calculated and used in the modeling of the oxidation dynamics. The model results are in good agreement with the experimental data over the entire temperature and time ranges studied.

A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor (MOS) capacitor configuration integrated into silicon-on-insulator (SOI).Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure,which boosts the modulation efficiency compared with a single MOS capacitor.The simulation results demonstrate that the VπLπ product is 2.4V·cm.The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve,respectively,indicating a bandwidth of 8GHz.The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Experimental Study on the Subthreshold Swing of Silicon Nanowire Transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I-ON) and off-current (I-OFF) of the fabricated silicon nanowire FET are 0.59 mu A and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mVN respectively due to the 30 nm thick gate oxide and 1015 cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.

Effects of helium and oxygen common implantation in silicon wafer

Defect engineering for SiO2] precipitation is investigated using He-ion implantation as the first stage of separation by implanted oxygen (STMOX). Cavities are created in Si by implantation with helium ions. After thermal annealing at different temperatures, the sample is implanted with 120keV 8.0 x 10(16) cm(-2) O ions. The O ion energy is chosen such that the peak of the concentration distribution is centred at the cavity band. For comparison, another sample is implanted with O ions alone. Cross-sectional transmission electron microscopy (XTEM), Fourier transform infrared absorbance spectrometry (FTIR) and atomic force microscopy (AFM) measurements are used to investigate the samples. The results show that a narrow nano-cavity layer is found to be excellent nucleation sites that effectively assisted SiO2 formation and released crystal lattice strain associated with silicon oxidation.

Study of He-induced nano-cavities as sinks of oxygen for forming silicon-on-insulator

In the present work, a Cz-Silicon wafer is implanted with helium ions to produce a buried porous layer, and then thermally annealed in a dry oxygen atmosphere to make oxygen transport into the cavities. The formation of the buried oxide layer in the case of internal oxidation (ITOX) of the buried porous layer of cavities in the silicon sample is studied by positron beam annihilation (PBA). The cavities are formed by 15 keV He implantation at a fluence of 2 x 10(16) cm(-2) and followed by thermal annealing at 673 K for 30 min in vacuum. The internal oxidation is carried out at temperatures ranging from 1073 to 1473 K for 2 h in a dry oxygen atmosphere. The layered structures evolved in the silicon are detected by using the PBA and the thicknesses of their layers and nature are also investigated. It is found that rather high temperatures must be chosen to establish a sufficient flux of oxygen into the cavity layer. On the other hand high temperatures lead to coarsening the cavities and removing the cavity layer finally.

Autophobic Dewetting of a Poly(methyl methacrylate) Thin Film on a Silicon Wafer Treated in Good Solvent Vapor

The wettability of thin poly(methyl methacrylate) (PMMA) films on a silicon wafer with a native oxide layer exposed to solvent vapors is dependent on the solvent properties. In the nonsolvent vapor, the film spread on the substrate with some protrusions generated on the film surface. In the good solvent vapor, dewetting happened. A new interface formed between the anchored PMMA chains and the swollen upper part of the film. Entropy effects caused the upper movable chains to dewet on the anchored chains. The rim instability depended on the surface tension of solvent (i.e., the finger was generated in acetone vapor (gamma(acetone) = 24 mN/m), not in dioxane vapor (gamma(dioxane) = 33 mN/m)). The spacing (lambda) that grew as an exponential function of film thickness h scaled as similar to h(1.31) whereas the mean size (D) of the resulting droplets grew linearly with h.

Crystal Growth Transition from Flat-On to Edge-On Induced by Solvent Evaporation in Ultrathin Films of Polystyrene-b-Poly(ethylene oxide)

The transition of lamellar crystal orientation from flat-on to edge-on in ultrathin films of polystyrene-b-poly(ethylene oxide) (PS-b-PEO) via solvent vapor (toluene) treatment Was investigated. When the as-prepared film was treated in saturated solvent vapor, breakout crystals could form quickly, and then they transformed from square single crystals (flat-on lamellae) to dendrites and finally to nanowire crystals (edge-on lamellae). Initially, heterogeneous nucleation tit the polymer/substrate interface dominated the structure evolution, leading to flat-on lamellar crystals orientation. And the transition from faceted habits to dendrites indicated a transition of underlying mechanism from nucleation-controlled to diffusion-limited growth. As the solvent molecules gradually diffused into the polymer/substrate interface, it will subsequently weaken the polymer-substrate interaction.

Kinetics of atomic force microscope-based scanned probe oxidation on an octadecylated silicon(111) surface

Atomic force microscope (AFM)-based scanned probe oxidation (SPO) nanolithography has been carried out on an octadecyl-terminated Si(111) surface to create dot-array patterns under ambient conditions in contact mode. The kinetics investigations indicate that this SPO process involves three stages. Within the steadily growing stage, the height of oxide dots increases logarithmically with pulse duration and linearly with pulse voltage. The lateral size of oxide dots tends to vary in a similar way. Our experiments show that a direct-log kinetic model is more applicable than a power-of-time law model for the SPO process on an alkylated silicon in demonstrating the dependence of oxide thickness on voltage exposure time within a relatively wide range. In contrast with the SPO on the octodecysilated SiO2/silicon surface, this process can be realized by a lower voltage with a shorter exposure time, which will be of great benefit to the fabrication of integrated nanometer-sized electronic devices on silicon-based substrates. This study demonstrates that the alkylated silicon is a new promising substrate material for silicon-based nanolithography.

Scanned probe oxidation on an octadecyl-terminated silicon (111) surface with an atomic force microscope: kinetic investigations in line patterning

Scanned probe oxidation (SPO) nanolithography has been performed with an atomic force microscope (AFM) on an octadecyl-terminated silicon (111) surface to create protuberant oxide line patterns under ambient conditions in contact mode. The kinetic investigations of this SPO process indicate that the oxide line height increases linearly with applied voltage and decreases logarithmically with writing, speed. The oxide line width also tends to vary with the same law. The ambient humidity and the AFM tip state can remarkably influence this process, too. As compared with traditional octadecylsilated SiO2/Si substrate, such a substrate can guarantee the SPO with an obviously lowered voltage and a greatly increased writing speed. This study demonstrates that such alkylated silicon is a promising silicon-based substrate material for SPO nanolithography.

Formation and characterisation of ordered porous vanadium oxide inverse opal materials for Li-ion batteries

This thesis presents several routes towards achieving artificial opal templates by colloidal self-assembly of polystyrene (PS) or poly(methyl methacrylate) (PMMA) spheres and the use of these template for the fabrication of V2O5 inverse opals as cathode materials for lithium ion battery applications. First, through the manipulation of different experimental factors, several methods of affecting or directing opal growth towards realizing different structures, improving order and/or achieving faster formation on a variety of substrates are presented. The addition of the surfactant sodium dodecyl sulphate (SDS) at a concentration above the critical micelle concentration for SDS to a 5 wt% solution of PMMA spheres before dip-coating is presented as a method of achieving ordered 2D PhC monolayers on hydrophobic Au-coated silicon substrates at fast and slow rates of withdrawal. The effect that the degree of hydrophilicity of glass substrates has on the ordering of PMMA spheres is next investigated for a slow rate of withdrawal under noise agitation. Heating of the colloidal solution is also presented as a means of affecting order and thickness of opal deposits formed using fast rate dip coating. E-beam patterned substrates are shown as a means of altering the thermodynamically favoured FCC ordering of polystyrene spheres (PS) when dip coated at slow rate. Facile routes toward the synthesis of ordered V2O5 inverse opals are presented with direct infiltration of polymer sphere templates using liquid precursor. The use of different opal templates, both 2D and 3D partially ordered templates, is compared and the composition and arrangement of the subsequent IO structures post infiltration and calcination for various procedures is characterised. V2O5 IOs are also synthesised by electrodeposition from an aqueous VOSO4 solution at constant voltage. Electrochemical characterisation of these structures as cathode material for Li-ion batteries is assessed in a half cell arrangement for samples deposited on stainless steel foil substrates. Improved rate capabilities are demonstrated for these materials over bulk V2O5, with the improvement attributed to the shorter Li ion diffusion distances and increased electrolyte infiltration provided by the IO structure.

Facet-embedded thin-film III-V edge-emitting lasers integrated with SU-8 waveguides on silicon.

A thin-film InGaAs/GaAs edge-emitting single-quantum-well laser has been integrated with a tapered multimode SU-8 waveguide onto an Si substrate. The SU-8 waveguide is passively aligned to the laser using mask-based photolithography, mimicking electrical interconnection in Si complementary metal-oxide semiconductor, and overlaps one facet of the thin-film laser for coupling power from the laser to the waveguide. Injected threshold current densities of 260A/cm(2) are measured with the reduced reflectivity of the embedded laser facet while improving single mode coupling efficiency, which is theoretically simulated to be 77%.

Germanium MOS Capacitors with Hafnium Dioxide and Silicon Dioxide Dielectrics

Germanium (Ge) does not grow a suitable oxide for MOS devices. The Ge/dielectric interface is of prime importance to the operation of photo-detectors and scaled MOSTs. Therefore there is a requirement for deposited or bonded dielectric materials. MOS capacitors have been formed on germanium substrates with three different dielectric materials. Firstly, a thermally grown and bonded silicon dioxide (SiO2) layer, secondly, SiO2 deposited by atmospheric pressure CVD ‘silox’, and thirdly a hafnium oxide (HfO2) high-k dielectric deposited by atomic layer deposition (ALD). Ge wafers used were p-type 1 0 0 2 O cm. C–V measurements have been made on all three types of capacitors to assess the interface quality. ALD HfO2 and silox both display acceptable C–V characteristics. Threshold voltage and maximum and minimum capacitance values closely match expected values found through calculation. However, the bonded SiO2 has non-ideal C–V characteristics, revealing the presence of a high density of interface states. A H2/N2 post metal anneal has a detrimental effect on C–V characteristics of HfO2 and silox dielectrics, causing a shift in the threshold voltage and rise in the minimum capacitance value. In the case of hafnium dioxide, capacitor properties can be improved by performing a plasma nitridation of the Ge surface prior to dielectric deposition.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.