Infrastructure and the Architectures of Modernity in Ireland 1916-2016

At the formation of the new Republic of Ireland, the construction of new infrastructures was seen as an essential element in the building of the new nation, just as the adoption of international style modernism in architecture was perceived as a way to escape the colonial past. Accordingly, infrastructure became the physical manifestation, the concrete identity of these objectives and architecture formed an integral part of this narrative. Moving between scales and from artefact to context, Infrastructure and the Architectures of Modernity in Ireland 1916-2016 provides critical insights and narratives on what is a complex and hitherto overlooked landscape, one which is often as much international as it is Irish. In doing so, it explores the interaction between the universalising and globalising tendencies of modernisation on one hand and the textures of local architectures on the other.

The book shows how the nature of technology and infrastructure is inherently cosmopolitan. Beginning with the building of the heroic Shannon hydro-electric facility at Ardnacrusha by the German firm of Siemens-Schuckert in the first decade of independence, Ireland became a point of varying types of intersection between imported international expertise and local need. Meanwhile, at the other end of the century, by the year 2000, Ireland had become one of the most globalized countries in the world, site of the European headquarters of multinationals such as Google and Microsoft. Climatically and economically expedient to the storing and harvesting of data, Ireland has subsequently become a repository of digital information farmed in large, single-storey sheds absorbed into anonymous suburbs. In 2013, it became the preferred site for Intel to design and develop its new microprocessor chip: the Galileo. The story of the decades in between, of shifts made manifest in architecture and infrastructure from the policies of economic protectionism, to the opening up of the country to direct foreign investment and the embracing of the EU, is one of the influx of technologies and cultural references into a small country on the edges of Europe as Ireland became both a launch-pad and testing ground for a series of aspects of designed modernity.

Dublin’s ephemeral and imaginary architectures

In 1989, the Irish architectural practice O’Donnell and Tuomey were commissioned to build a temporary pavilion to represent Ireland at the 11 Cities/11 Nations exhibition at Leeuwarden in the Netherlands. Citing Peter Smithson, John Tuomey suggested the pavilion, which drew inspirations from the forms and materials of the modern Irish barn, embodied an intention ‘not just to build but to communicate’. Its subsequent reassembly for the inauguration of the Irish Museum of Modern Art in the courtyard of the seventeenth-century Royal Hospital Kilmainham in Dublin in 1991, drew comparisons between the urban sophistication of this colonial building, its svelte new refit, and the rural expression of O’Donnell + Tuomey’s barn. It was, one critic recently noted, as if ‘a wedding had been crashed by a country cousin who had forgotten to clean his boots’.
It has been argued that temporary or ephemeral pieces of architecture, unburdened by the traditional constraints of firmitas or utilitas, have the ability to offer a concise distillation of meaning and intention. Approaching the qualities of rhetoric, such architectures share similarities with the monument and yet differ in fundamental ways. Their rapid construction in lightweight materials can allow for an almost instantaneous negotiation of zeitgeist. And, unlike the monument, from the outset the space and form of these installations is designed to disappear.
This paper analyses the ephemeral architectures of Dublin in the modern period contextualising their qualities and intentions as they manifest themselves across colonial, post-colonial and contemporary epochs. It finds origins in the theatrical sets of the late eighteenth century and traces their movements into the semi-public sphere of the pleasure garden and finally into the theatre of the streets. It is here that temporary architecture in the city has been at its most potent, allowing the amplification or subversion of the meanings of much larger spaces. Historically, much of Dublin’s most conspicuous instances of ephemeral architecture have been realised as a means of articulating mass spectacle in political, religious or nationalistic events. And while much of this has sought to confirm dominant ideologies, it has also been possible to discern moments of opposition.
The contemporary period, however, has arguably witnessed a shift in ephemeral architectures from explicitly representing ‘positive ideologies’ towards something more oblique or nebulous. This turn towards abstraction in form and space has rendered an especially communicative form of architecture particularly elusive. By examining continuities within the apparent disjuncture between historical and contemporary examples, this paper begins to unpick the language of recent ephemeral architecture in Dublin and situate it within wider global trends where political and economic imperatives are often simultaneously obscured and expressed in public space by a vocabulary of universality. As Jurgen Habermas has suggested, the contemporary value given to the transitory and the ephemeral ‘discloses a longing for an undefiled, immaculate and stable present’.

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

HpMC: An Energy- Aware Management System for Multi-Level Memory Architectures

DRAM technology faces density and power challenges to increase capacity because of limitations of physical cell design. To overcome these limitations, system designers are exploring alternative solutions that combine DRAM and emerging NVRAM technologies. Previous work on heterogeneous memories focuses, mainly, on two system designs: PCache, a hierarchical, inclusive memory system, and HRank, a flat, non-inclusive memory system. We demonstrate that neither of these designs can universally achieve high performance and energy efficiency across a suite of HPC workloads. In this work, we investigate the impact of a number of multilevel memory designs on the performance, power, and energy consumption of applications. To achieve this goal and overcome the limited number of available tools to study heterogeneous memories, we created HMsim, an infrastructure that enables n-level, heterogeneous memory studies by leveraging existing memory simulators. We, then, propose HpMC, a new memory controller design that combines the best aspects of existing management policies to improve performance and energy. Our energy-aware memory management system dynamically switches between PCache and HRank based on the temporal locality of applications. Our results show that HpMC reduces energy consumption from 13% to 45% compared to PCache and HRank, while providing the same bandwidth and higher capacity than a conventional DRAM system.

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

On the performance of LDPC and turbo decoder architectures with unreliable memories

In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.

Computing probable maximum loss in catastrophe reinsurance portfolios on multi-core and many-core architectures

In the reinsurance market, the risks natural catastrophes pose to portfolios of properties must be quantified, so that they can be priced, and insurance offered. The analysis of such risks at a portfolio level requires a simulation of up to 800 000 trials with an average of 1000 catastrophic events per trial. This is sufficient to capture risk for a global multi-peril reinsurance portfolio covering a range of perils including earthquake, hurricane, tornado, hail, severe thunderstorm, wind storm, storm surge and riverine flooding, and wildfire. Such simulations are both computation and data intensive, making the application of high-performance computing techniques desirable.

In this paper, we explore the design and implementation of portfolio risk analysis on both multi-core and many-core computing platforms. Given a portfolio of property catastrophe insurance treaties, key risk measures, such as probable maximum loss, are computed by taking both primary and secondary uncertainties into account. Primary uncertainty is associated with whether or not an event occurs in a simulated year, while secondary uncertainty captures the uncertainty in the level of loss due to the use of simplified physical models and limitations in the available data. A combination of fast lookup structures, multi-threading and careful hand tuning of numerical operations is required to achieve good performance. Experimental results are reported for multi-core processors and systems using NVIDIA graphics processing unit and Intel Phi many-core accelerators.

Designing Bare Essentials: Aldi, Lidle and the architectures of cheapness

They’re cheap. They’re in every settlement of significance in Britain, Ireland and elsewhere. We all use them but perhaps do not always admit to it. Especially, if we are architects.
Over the past decades Aldi/Lidl low cost supermarkets have escaped from middle Europe to take over large tracts of the English speaking world remaking them according to a formula of mass-produced sheds, buff-coloured cobble-lock car parks, logos in primary colours, bare-shelves and eclectic special offers. Response within architectural discourse to this phenomenon has been largely one of indifference and such places remain, perhaps reiterating Pevsner’s controversial insights into the bicycle shed, on the peripheries of what we might term architecture. This paper seeks to explore the spatial complexities of the discount supermarket and in doing so open up a discussion on the architecture of cheapness. As a road-map, it takes former managing director Dieter Brandes’ treatise on the Aldi formula, Bare Essentials: the Aldi Way to Retailing, and investigates the strategies through which economic exigencies manifest themselves in a series of spatial tactics which involve building. Central to this is the idea of architecture as system rather than form and, in Aldi/Lidl’s case, the result of a spatial network of flows. To understand the architecture of the supermarket, then, it is necessary to measure the times and spaces of supply across the scales of intersection between global and local.
Evaluating the energy, economy and precision of such systems challenges the liminal position of the commercial, the placeless and especially the cheap within architectural discourse. As is well known, architectures of mass-production and prefabrication and their origins exercised modernist thinkers such as Sigfried Giedion and Walter Gropius in the early twentieth century and has undergone a resurgence in recent times. Meanwhile, the mapping of the hitherto overlooked forms and iconography of commerce in Learning from Las Vegas (1971) was extended by Rem Koolhaas et al into an investigation of the technologies, systems and precedents of retail in the Harvard Design School Guide to Shopping, thirty years later in 2001. While obviously always a criteria for building, to find writings on architecture which explicitly celebrate cheapness as a design virtue or, indeed, even iterate the word cheap is more difficult. Walter Gropius’ essay ‘How can we build cheaper, better, more attractive houses?’ (1927), however, situates the cheap within the discussions – articulated, amongst others, by Karl Teige and Bruno Taut – surrounding the minimal dwelling and the moral benefits of absence of the 1920s and 30s.
In our contemporary age of heightened consumption, it is perhaps fitting that an architecture of bare essentials is defined in retail rather than in housing, a commercial existenzminimum where the Miesian paradox of ‘less is more’ is resold as a paradigm of ‘more for less’ in the ubiquitous yet overlooked architectures of the discount supermarket.

Study of the impact from nonlinear distortion in radio receiver architectures

A dissertação de doutoramento apresentada insere-se na área de electrónica não-linear de rádio-frequência (RF), UHF e microondas, tendo como principal campo de acção o estudo da distorção nãolinear em arquitecturas de recepção rádio, nomeadamente receptores de conversão directa como Power Meters, RFID (Radio Frequency IDentification) ou SDR (Software Define Radio) front-ends. Partindo de um estudo exaustivo das actuais arquitecturas de recepção de radiofrequência e revendo todos os conceitos teóricos relacionados com o desempenho não-linear dos sistemas/componentes electrónicos, foram desenvolvidos algoritmos matemáticos de modulação dos comportamentos não-lineares destas arquitecturas, simulados e testados em laboratório e propostas novas arquitecturas para a minimização ou cancelamento do impacto negativo de grandes interferidores em frequências vizinhas ao do sistema pretendido.

Multi-standard reconfigurable wireless transmitter architectures

The continuous demand for highly efficient wireless transmitter systems has triggered an increased interest in switching mode techniques to handle the required power amplification. The RF carrier amplitude-burst transmitter, i.e. a wireless transmitter chain where a phase-modulated carrier is modulated in amplitude in an on-off mode, according to some prescribed envelope-to-time conversion, such as pulse-width or sigma-delta modulation, constitutes a promising architecture capable of efficiently transmitting signals of highly demanding complex modulation schemes. However, the tested practical implementations present results that are way behind the theoretically advanced promises (perfect linearity and efficiency). My original contribution to knowledge presented in this thesis is the first thorough study and model of the power efficiency and linearity characteristics that can be actually achieved with this architecture. The analysis starts with a brief revision of the theoretical idealized behavior of these switched-mode amplifier systems, followed by the study of the many sources of impairments that appear when the real system is implemented. In particular, a special attention is paid to the dynamic load modulation caused by the often ignored interaction between the narrowband signal reconstruction filter and the usual single-ended switched-mode power amplifier, which, among many other performance impairments, forces a two transistor implementation. The performance of this architecture is clearly explained based on the presented theory, which is supported by simulations and corresponding measured results of a fully working implementation. The drawn conclusions allow the development of a set of design rules for future improvements, one of which is proposed and verified in this thesis. It suggests a significant modification to this traditional architecture, where now the phase modulated carrier is always on – and thus allowing a single transistor implementation – and the amplitude is impressed into the carrier phase according to a bi-phase code.

Preface to the special section on algorithms and architectures for real-time control

Rapid developments in microelectronics and computer science continue to fuel new opportunities for real-time control engineers. The ever-increasing system complexity and sophistication, environmental legislation, economic competition, safety and reliability constitute some of the driving forces for the research themes presented at the IFAC Workshop on Algorithms and Architectures for Real-Time Control (AARTC'2000). The Spanish Society for Automatic Control hosted AARTC'2000, which was held at Palma de Maiorca, Spain, from 15 to 17 May. This workshop was the sixth in the series.

Algorithms and architectures for real-time control

Algorithm and Architectures for Real-Time Control Workshop had the objective to investigate the state of the art and to present new research and application results in software and hardware for real-timecontrol, as well as to bring together engeneers and computer scientists who are researchers, developers and practitioners, both from the academic and the industrial world.