Energy efficiency in gait, activity, participation, and health status in children with cerebral palsy

The aim of the study was to establish if a relationship exists between the energy efficiency of gait, and measures of activity limitation, participation restriction, and health status in a representative sample of children with cerebral palsy (CP). Secondary aims were to investigate potential differences between clinical subtypes and gross motor classification, and to explore other relationships between the measures under investigation. A longitudinal study of a representative sample of 184 children with ambulant CP was conducted (112 males, 72 females; 94 had unilateral spastic C P, 84 had bilateral spastic C P, and six had non-spastic forms; age range 4-17y; Gross Motor Function Classification System Level I, n=57; Level II, n=91; Level III, n=22; and Level IV, n=14); energy efficiency (oxygen cost) during gait, activity limitation, participation restriction, and health status were recorded. Energy efficiency during gait was shown to correlate significantly with activity limitations; no relationship between energy efficiency during gait was found with either participation restriction or health status. With the exception of psychosocial health, all other measures showed significant differences by clinical subtype and gross motor classification. The energy efficiency of walking is not reflective of participation restriction or health status. Thus, therapies leading to improved energy efficiency may not necessarily lead to improved participation or general health.

The Macroeconomic Factors Conditioning the Impact of Identity on Attitudes towards the EU

Factors relating to identity and to economics have been shown to be important predictors of attitudes towards the European Union (EU). In this article, we show that the impact of identity is conditional on economic context. First, living in a member state that receives relatively high levels of EU funding acts as a 'buffer', diluting the impact of an exclusive national identity on Euroscepticism. Second, living in a relatively wealthy member state, with its associated attractiveness for economic migrants, increases the salience of economic xenophobia as a driver of sceptical attitudes. These results highlight the importance of seeing theories of attitude formation (such as economic and identity theories) not as competitors but rather as complementary, with the predictive strength of one theoretical approach (identity) being a function of system-level variation in factors relating to the other theoretical approach (macro-level economic conditions).

Power Efficient Dynamic-Range Utilisation for DSP On FPGA

A power and resource efficient ‘dynamic-range utilisation’ technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data epresentation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.

Power Efficient DSP Datapath Configuration Methodology for FPGA

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

Memory-Centric Hardware Synthesis from Dataflow Models

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.

Incremental learning from stream data

Recent years have witnessed an incredibly increasing interest in the topic of incremental learning. Unlike conventional machine learning situations, data flow targeted by incremental learning becomes available continuously over time. Accordingly, it is desirable to be able to abandon the traditional assumption of the availability of representative training data during the training period to develop decision boundaries. Under scenarios of continuous data flow, the challenge is how to transform the vast amount of stream raw data into information and knowledge representation, and accumulate experience over time to support future decision-making process. In this paper, we propose a general adaptive incremental learning framework named ADAIN that is capable of learning from continuous raw data, accumulating experience over time, and using such knowledge to improve future learning and prediction performance. Detailed system level architecture and design strategies are presented in this paper. Simulation results over several real-world data sets are used to validate the effectiveness of this method.

Defining a Research Agenda in Value Driven Design: Questions That Need to be Asked

Value driven design is an innovative design process that utilizes the optimization of a system level value function to determine the best possible design. This contrasts with more traditional systems engineering techniques, which rely on satisfying requirements to determine the design solution. While ‘design for value’ is intuitively acceptable, the transformation of value driven design concepts into practical tools and methods for its application is challenging. This, coupled with the growing popularity of value-centric design philosophies, has led to a proposed research agenda in value driven design. This research agenda asks fundamental questions about the design philosophy and attempts to identify areas of significant challenge. The research agenda is meant to stimulate discussion in the field, as well as prompt research that will lead to the development of tools and methodologies that will facilitate the application of value driven design and further the state of the art.

Free-space optoelectronic switching cores with MPLS for SANs over WDM ring networks

With increasing demands on storage devices in the modern communication environment, the storage area network (SAN) has evolved to provide a direct connection allowing these storage devices to be accessed efficiently. To optimize the performance of a SAN, a three-stage hybrid electronic/optical switching node architecture based on the concept of a MPLS label switching mechanism, aimed at serving as a multi-protocol label switching (MPLS) ingress label edge router (LER) for a SAN-enabled application, has been designed. New shutter-based free-space multi-channel optical switching cores are employed as the core switch fabric to solve the packet contention and switching path conflict problems. The system-level node architecture design constraints are evaluated through self-similar traffic sourced from real gigabit Ethernet network traces and storage systems. The extension performance of a SAN over a proposed WDM ring network, aimed at serving as an MPLS-enabled transport network, is also presented and demonstrated.

Millimetre-wave broadband wireless systems and enabling MMIC technologies

Chapter eleven on Mm-wave broadband wireless systems and enabling MMIC technologies, is contributed by Jian Zhang, Mury Thian, Guochi Huang, George Goussetis and Vincent F. Fusco, from Queen's University Belfast, UK. Millimeter wave bands provide large available bandwidths for high data rate wireless communication systems, which are envisaged to shift data throughput well in the GBps range. This capability has over past few years driven rapid developments in the technology underpinning broadband wireless systems as well as in the standardisation activity from various non-governmental consortia and the band allocation from spectrum regulators globally. This chapter provides an overview of the recent developments on V-band broadband wireless systems with the emphasis placed on enabling MMIC technologies. An overview of the key applications and available standards is presented. System-level architectures for broadband wireless applications are being reviewed. Examples of analysis, design and testing on MMIC components in SiGe BiCMOS are presented and the outlook of the technology is discussed.

Coordination of palliative cancer care in the community: "unfinished business"

Goal: This study assessed the degree to which services in south-central Ontario, Canada, were coordinated to meet the supportive care needs of palliative cancer patients and their families. Participants and method: Programs within the region that were identified as providing supportive care to palliative cancer patients and their families were eligible to participate in the study. Program administrators participated in a semi-structured interview and direct-care providers completed a survey instrument. Main results: Administrators from 37 (97%) of 38 eligible programs and 109 direct-care providers representing 26 (70%) programs participated in the study. Most administrator and direct-care respondents felt that existing services in the community were responsive to palliative care patients' individual needs. However, at a system level, most respondents in both groups felt that required services were not available and that resources were inadequate. The most frequently reported unmet supportive care need identified by both respondent groups was psychological/social support. Most administrator (69%) and direct-care (64%) respondents felt that palliative care services were not available when needed. The majority of administrator and direct-care respondents were satisfied with the exchange of patient information within and between programs, although direct-care staff identified a deficit in information transferred on palliative care patients' social/psychological status. Conclusions: The study demonstrated the value of a theory-based approach to evaluate the coordination of palliative cancer care services. The findings revealed that service programs faced significant challenges in their efforts to provide coordinated care. © 2009 Springer-Verlag.

Generic low-latency NoC router architecture for FPGA computing systems

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems. © 2011 IEEE.

Novel Radio Link Buffer Management Schemes for End-User Multi-class Traffic in High Speed Packet Access Networks

The requirement to provide multimedia services with QoS support in mobile networks has led to standardization and deployment of high speed data access technologies such as the High Speed Downlink Packet Access (HSDPA) system. HSDPA improves downlink packet data and multimedia services support in WCDMA-based cellular networks. As is the trend in emerging wireless access technologies, HSDPA supports end-user multi-class sessions comprising parallel flows with diverse Quality of Service (QoS) requirements, such as real-time (RT) voice or video streaming concurrent with non real-time (NRT) data service being transmitted to the same user, with differentiated queuing at the radio link interface. Hence, in this paper we present and evaluate novel radio link buffer management schemes for QoS control of multimedia traffic comprising concurrent RT and NRT flows in the same HSDPA end-user session. The new buffer management schemes—Enhanced Time Space Priority (E-TSP) and Dynamic Time Space Priority (D-TSP)—are designed to improve radio link and network resource utilization as well as optimize end-to-end QoS performance of both RT and NRT flows in the end-user session. Both schemes are based on a Time-Space Priority (TSP) queuing system, which provides joint delay and loss differentiation between the flows by queuing (partially) loss tolerant RT flow packets for higher transmission priority but with restricted access to the buffer space, whilst allowing unlimited access to the buffer space for delay-tolerant NRT flow but with queuing for lower transmission priority. Experiments by means of extensive system-level HSDPA simulations demonstrates that with the proposed TSP-based radio link buffer management schemes, significant end-to-end QoS performance gains accrue to end-user traffic with simultaneous RT and NRT flows, in addition to improved resource utilization in the radio access network.

End-to-End QoS Enhancement ofHSDPA End-User Multi-flow Traffic Using RAN Buffer Management

High speed downlink packet access (HSDPA) was introduced to UMTS radio access segment to provide higher capacity for new packet switched services. As a result, packet switched sessions with multiple diverse traffic flows such as concurrent voice and data, or video and data being transmitted to the same user are a likely commonplace cellular packet data scenario. In HSDPA, radio access network (RAN) buffer management schemes are essential to support the end-to-end QoS of such sessions. Hence in this paper we present the end-to-end performance study of a proposed RAN buffer management scheme for multi-flow sessions via dynamic system-level HSDPA simulations. The scheme is an enhancement of a time-space priority (TSP) queuing strategy applied to the node B MAC-hs buffer allocated to an end user with concurrent real-time (RT) and non-real-time (NRT) flows during a multi-flow session. The experimental multi- flow scenario is a packet voice call with concurrent TCP-based file download to the same user. Results show that with the proposed enhancements to the TSP-based RAN buffer management, end-to-end QoS performance gains accrue to the NRT flow without compromising RT flow QoS of the same end user session

A Dynamic Buffer Management Scheme for End-to-End QoS Enhancement of Multi-flow Services in HSDPA

End-user multi-flow services support is a crucial aspect of current and next generation mobile networks. This paper presents a dynamic buffer management strategy for HSDPA end-user multi-flow traffic with aggregated real-time and non-real-time flows. The scheme incorporates dynamic priority switching between the flows for transmission on the HSDPA radio channel. The end-to-end performance of the proposed strategy is investigated with an end-user multi-flow session of simultaneous VoIP and TCP-based downlink traffic using detailed HSDPA system-level simulations. Compared to an equivalent static buffer management scheme, the results show that end-to-end throughput performance gains in the non-real-time flow and better HSDPA channel utilization is attainable without compromising the real-time VoIP flow QoS constraints

TLM2.0 based timing accurate modeling method for complex NoC systems

Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE.