Evaluation of the presence of microorganisms in solid-organ preservation solution

OBJECTIVE: To assess the presence of microorganism contamination in the preservation solution for transplant organs (kidney/pancreas). Method: Between August 2007 and March 2008, 136 samples of preservation solution were studied prior to graft implantation. Variables related to the donor and to the presence of microorganisms in the preservation solution of organs were evaluated, after which the contamination was evaluated in relation to the recipient culture variable. Univariate and multivariate statistical analyses were performed. RESULTS: The contamination rate of the preservation solution was 27.9%. Coagulase-negative Staphylococcus was the most frequently isolated microorganism. However, highly virulent agents, such as fungi and enterobacteria, were also isolated. In univariate analysis, the variable donor antibiotic use was significantly associated to the contamination of the preservation solution. on the other hand, multivariate analysis found statistical significance in donor antibiotic use and donor's infectious complications variables. CONCLUSIONS: In this study, 27.9% of the preservation solutions of transplant organs were contaminated. Infectious diseases and non-use of antibiotics by the donor were significantly related to the presence of microorganisms in organ preservation solutions. Contamination in organ preservation solutions was not associated with infection in the recipient.

Production of α-amilase by solid state fermentation by Rhizopus oryzae

A thermotolerant strain of Rhizopus oryzae was grown in three agro-industrial by-products: brewers’ rice, corn grits and wheat bran. Different substrates, cultivation time, moisture content, additional nitrogen sources, pH and temperature of incubation were evaluated aiming to optimize growing conditions. The highest enzymatic activity was observed after 24 h of cultivation using wheat bran as substrate with the following salt solutions: NH4NO3, MgSO4.7H2O and (NH4)2SO4 0.1% at temperature of 35°C. It was observed that changes in the pH range 4.0-6.0 did not significantly affect α-amylase activity. The optimum operation conditions were 75°C and pH 4.5. The enzymes remained stable at 75°C in the absence of substrate for 25 min.

Orange opals from Buriti dos Montes, Piauí: solid inclusions as genetic guides

As opalas laranjas de Buriti dos Montes (Piauí, nordeste do Brasil) têm propriedades gemológicas que favorecem seu uso como jóias; essas características incluem as cores, transparência, dureza e estabilidade relativamente elevadas. O exótico conteúdo de inclusões sólidas proporciona maior beleza às opalas da região. Essas opalas foram originadas por processos hidrotermais e são encontradas, principalmente, em vênulas e veios nos arenitos do Grupo Serra Grande, seccionados por soleiras e diques de diabásio da Formação Sardinha. Inclusões sólidas, tais como bolhas, agregados botrioidais, dendritos e nódulos, entre outras, consistem, principalmente, de caulinita, hematita/goethita e quartzo e influenciam a composição química das opalas. O zoneamento intenso dos cristais de quartzo e os elevados valores de Ba e Fe sugerem que os depósitos de opala foram formados em ambiente hidrotermal. Os diques de diabásio teriam sido responsáveis pelo aquecimento dos fluidos hidrotermais. Os arenitos, ricos em soluções aquosas, também teriam contribuído com a sílica disponível para a saturação dessas soluções e as fraturas permitiram a migração e aprisionamento dos fluidos hidrotermais, resultando nos veios mineralizados.

Management of Port Solid Waste Framework

One of contemporary environmental issues refers to progressive and diverse generation of solid waste in urban areas or specific, and requires solutions because the traditional methods of treatment and disposal are becoming unviable over the years and, consequently, a significant contingent of these wastes presents final destination inappropriate. The diversity of solid waste generated as a result of human activities must have the appropriate allocation to specific legislation in force, such as landfill, incineration, among other procedures established by the competent bodies. Thus, also the waste generated in port activities or proceeding vessels require classification and segregation for proper disposal later. This article aims at presenting a methodology for the collection, transportation, treatment and disposal of solid waste port and also application of automation technology that makes possible the implementation of the same.

Probing unoccupied electronic states in aqueous solutions

Water is one of the most common compounds on earth and is essential for all biological activities. Water has, however, been a mystery for many years due to the large number of unusual chemical and physical properties, e.g. decreased volume during melting and maximum density at 4 °C. The origin of the anomalies behavior is the nature of the hydrogen bond. This thesis will presented an x-ray absorption spectroscopy (XAS) study to reveal the hydrogen bond structure in liquid water. The x-ray absorption process is faster than a femtosecond and thereby reflects the molecular orbital structure in a frozen geometry locally around the probed water molecules. The results indicate that the electronic structure of liquid water is significantly different from that of the solid and gaseous forms. The molecular arrangement in the first coordination shell of liquid water is actually very similar as the two-hydrogen-bonded configurations at the surface of ice. This discovery suggests that most molecules in liquid water have two-hydrogen-bonded configurations with one donor and one acceptor hydrogen bond compared to the four-hydrogen-bonded tetrahedral structure in ice. This result is controversial since the general picture is that the structure of liquid water is very similar to the structure of ice. The results are, however, consistent with x-ray and neutron diffraction data but reveals serious discrepancies with structures based on current molecular dynamics simulations. The two-hydrogen-bond configuration in liquid water is rigid and heating from 25 °C to 90 °C introduce a minor change in the hydrogen-bonded configurations. Furthermore, XAS studies of water in aqueous solutions show that ion hydration does not affect the hydrogen bond configuration of the bulk. Only water molecules in the close vicinity to the ions show changes in the hydrogen bond formation. XAS data obtained with fluorescence yield are sensitive enough to resolved electronic structure of water molecules in the first hydration sphere and to distinguish between different protonated species. Hence, XAS is a useful tool to provide insight into the local electronic structure of a hydrogen-bonded liquid and it is applied for the first time on water revealing unique information of high importance.

Numerical simulation of ion transport through ion channels and solid-state nanopores

Ion channels are pore-forming proteins that regulate the flow of ions across biological cell membranes. Ion channels are fundamental in generating and regulating the electrical activity of cells in the nervous system and the contraction of muscolar cells. Solid-state nanopores are nanometer-scale pores located in electrically insulating membranes. They can be adopted as detectors of specific molecules in electrolytic solutions. Permeation of ions from one electrolytic solution to another, through a protein channel or a synthetic pore is a process of considerable importance and realistic analysis of the main dependencies of ion current on the geometrical and compositional characteristics of these structures are highly required. The project described by this thesis is an effort to improve the understanding of ion channels by devising methods for computer simulation that can predict channel conductance from channel structure. This project describes theory, algorithms and implementation techniques used to develop a novel 3-D numerical simulator of ion channels and synthetic nanopores based on the Brownian Dynamics technique. This numerical simulator could represent a valid tool for the study of protein ion channel and synthetic nanopores, allowing to investigate at the atomic-level the complex electrostatic interactions that determine channel conductance and ion selectivity. Moreover it will provide insights on how parameters like temperature, applied voltage, and pore shape could influence ion translocation dynamics. Furthermore it will help making predictions of conductance of given channel structures and it will add information like electrostatic potential or ionic concentrations throughout the simulation domain helping the understanding of ion flow through membrane pores.

Helix-coil-transition in solid polypeptides

Abstract Poly(L-glutamic acid) (PLGA) was synthesized by living anionic ring-opening polymerization of the NCA monomer, which was obtained by reacting diphosgene with an amino acid derivative. The chemical structures and thermal properties were characterized by 1H-NMR, 13C-NMR, TGA and DSC. XRD powder patterns found to be amorphous for all polymers obtained. The molecular weights could be determined under severe limitations due to low solubility and high aggregation tendency. The secondary structure of the PLGA films was analyzed in the solid state by IR spectroscopy; the order was determined mainly by XRD. Uniform bulk films (1-5 µm) were produced by drop-casting of PLGA solutions in TFA on silica. The XRD film analysis indicated the absence of a long range order or an orientation even if a helical microstructure was confirmed by IR spectroscopy. The coil solvent TFA delivered constantly a helical or a β-sheet structure in the solid state depending on the water content of the solvent which was observed for the first time to exhibit a high influence on the crystallization process for PLGA. Temperature dependent in-situ IR measurements were examined to analyze if a helix-coil transition occurs, but there could be no solvent system determined, which resulted in a disordered coil structure in the solid state. General parameters like solvent systems, evaporation conditions, concentration, substrates etc. were analyzed. New crystallizations were obtained on silica prepared by drop-casting of solutions of PLGA in DMF, DMA, TMU, NMP, and pyridine/water mixtures, respectively. PSCBC in DMF, CDCl3/TFA-d, and PSBC in CDCl3/TFA-d exhibited the same crystalline diffraction patterns like PLGA. The long range order in the X-ray diffraction pattern is proven by extremely sharp crystalline signals, which are not changing the shape or the position of the peak by increasing the temperature up to 160°C. The substrate seems to play a decisive role because the crystalline structures were not obtainable on glass. The crystal structure consists probably of two different layered structures based on the intensity ratios of the two series of crystalline signals in the X-ray diffraction patterns. The source of the layered structure remains unclear and needs further studies to investigate the spatial arrangement of the chains in more detail. The secondary structure was still not changing upon heating even if a highly crystalline diffraction pattern occurs. Concluding that even the newly investigated crystallization did not show a helix-coil transition in the solid state by annealing, the phenomenon known in solution has to be claimed as unachievable in the solid state based on the results of this work. A remaining open question represents the observation that the same crystalline pattern can be reproducibly prepared with exhibiting two different ordered secondary structures (helix and β-sheet). After the investigation that the evaporation time cannot be decisive for the crystal growth, the choice of a strong hydrogen bonding interrupting solvent is most probably the key to support and induce the crystallization process.

Drainage of thin aqueous films between solid surfaces measured with the colloidal probe technique

Understanding liquid flow at the vicinity of solid surfaces is crucial to the developmentrnof technologies to reduce drag. One possibility to infer flow properties at the liquid-solid interface is to compare the experimental results to solutions of the Navier-Stokes equations assuming the no-slip boundary condition (BC) or the slip BC. There is no consensus in the literature about which BC should be used to model the flow of aqueous solutions over hydrophilic surfaces. Here, the colloidal probe technique is used to systematically address this issue, measuring forces acting during drainage of water over a surface. Results show that experimental variables, especially the cantilever spring constant, lead to the discrepancy observed in the literature. Two different parameters, calculated from experimental variables, could be used to separate the data obtained in this work and those reported in the literature in two groups: one explained with the no-slip BC, and another with the slip BC. The observed residual slippage is a function of instrumental variables, showing a trend incompatible with the available physical justifications. As a result, the no-slip is the more appropriate BC. The parameters can be used to avoid situations where the no-slip BC is not satisfied.

Twelve factors influencing sustainable recycling of municipal solid waste in developing countries

Sustainable management of solid waste is a global concern, as exemplified by the United Nations Millennium Development Goals (MDG) that 191 member states support. The seventh MDG indirectly advocates for municipal solid waste management (MSWM) by aiming to ensure environmental sustainability into countries’ policies and programs and reverse negative environmental impact. Proper MSWM will likely result in relieving poverty, reducing child mortality, improving maternal health, and preventing disease, which are MDG goals one, four, five, and six, respectively (UNMDG, 2005). Solid waste production is increasing worldwide as the global society strives to obtain a decent quality of life. Several means exist in which the amount of solid waste going to a landfill can be reduced, such as incineration with energy production, composting of organic wastes, and material recovery through recycling, which are all considered sustainable methods by which to manage MSW. In the developing world, composting is already a widely-accepted method to reduce waste fated for the landfill, and incineration for energy recovery can be a costly capital investment for most communities. Therefore, this research focuses on recycling as a solution to the municipal solid waste production problem while considering the three dimensions of sustainability environment, society, and economy. First, twenty-three developing country case studies were quantitatively and qualitatively examined for aspects of municipal solid waste management. The municipal solid waste (MSW) generation and recovery rates, as well as the composition were compiled and assessed. The average MSW generation rate was 0.77 kg/person/day, with recovery rates varying from 5 – 40%. The waste streams of nineteen of these case studies consisted of 0 – 70% recyclable material and 17 – 80% organic material. All twenty-three case studies were analyzed qualitatively by identifying any barriers or incentives to recycling, which justified the creation of twelve factors influencing sustainable municipal solid waste management (MSWM) in developing countries. The presence of regulations, enforcement of laws, and use of incentive schemes constitutes the first factor, Government Policy. Cost of MSWM operations, the budget allocated to MSWM by local to national governments, as well as the stability and reliability of funds comprise the Government Finances factor influencing recycling in the third world. Many case studies indicated that understanding features of a waste stream such as the generation and recovery rates and composition is the first measure in determining proper management solutions, which forms the third factor Waste Characterization. The presence and efficiency of waste collection and segregation by scavengers, municipalities, or private contractors was commonly addressed by the case studies, which justified Waste Collection and Segregation as the fourth factor. Having knowledge of MSWM and an understanding of the linkages between human behavior, waste handling, and health/sanitation/environment comprise the Household Education factor. Individuals’ income influencing waste handling behavior (e.g., reuse, recycling, and illegal dumping), presence of waste collection/disposal fees, and willingness to pay by residents were seen as one of the biggest incentives to recycling, which justified them being combined into the Household Economics factor. The MSWM Administration factor was formed following several references to the presence and effectiveness of private and/or public management of waste through collection, recovery, and disposal influencing recycling activity. Although the MSWM Personnel Education factor was only recognized by six of the twenty-two case studies, the lack of trained laborers and skilled professionals in MSWM positions was a barrier to sustainable MSWM in every case but one. The presence and effectiveness of a comprehensive, integrative, long-term MSWM strategy was highly encouraged by every case study that addressed the tenth factor, MSWM Plan. Although seemingly a subset of private MSWM administration, the existence and profitability of market systems relying on recycled-material throughput, involvement of small businesses, middlemen, and large industries/exporters is deserving of the factor Local Recycled-Material Market. Availability and effective use of technology and/or human workforce and the safety considerations of each were recurrent barriers and incentives to recycling to warrant the Technological and Human Resources factor. The Land Availability factor takes into consideration land attributes such as terrain, ownership, and development which can often times dictate MSWM. Understanding the relationships among the twelve factors influencing recycling in developing countries, made apparent the collaborative nature required of sustainable MSWM. Factors requiring the greatest collaborative inputs include waste collection and segregation, MSWM plan, and local recycled-material market. Aligning each factor to the societal, environmental, and economic dimensions of sustainability revealed the motives behind the institutions contributing to each factor. A correlation between stakeholder involvement and sustainability existed, as supported by the fact that the only three factors driven by all three dimensions of sustainability were the same three that required the greatest collaboration with other factors. With increasing urbanization, advocating for improved health for all through the MDG, and changing consumption patterns resulting in increasing and more complex waste streams, the utilization of the collaboration web offered by this research is ever needed in the developing world. Through its use, the institutions associated with each of the twelve factors can achieve a better understanding of the collaboration necessary and beneficial for more sustainable MSWM.

Combined LARES-LAGEOS Solutions

LARES is a new spherical geodetic satellite designed for SLR observations. It is made of solid tungsten alloy covered with 92 corner cubes. Due to a very small area-to-mass ratio, the sensitivity of LARES orbits to non-gravitational forces is greatly minimized. We processed 82 weeks (Feb12-Aug13) of LARES observations from a global SLR network and we analyzed the contribution of LARES data to the current SLR products (e.g., global scale and geocenter coordinates). The quality of the combined LARES+LAGEOS-1/2 solutions is also addressed in the paper. Introduction LARES

Characterization cement pastes degraded in lanoratory solutions and physiochemical parameters employed for modeling the process

Previously degradation studies carried out, over a number of different mortars by the research team, have shown that observed degradation does not exclusively depend on the solution equilibrium pH, nor the aggressive anions relative solubility. In our tests no reason was found that could allow us to explain, why same solubility anions with a lower pH are less aggressive than others. The aim of this paper is to study cement pastes behavior in aggressive environments. As observed in previous research, this cement pastes behaviors are not easily explained only taking into account only usual parameters, pH, solubility etc. Consequently the paper is about studying if solution physicochemical characteristics are more important in certain environments than specific pH values. The paper tries to obtain a degradation model, which starting from solution physicochemical parameters allows us to interpret the different behaviors shown by different composition cements. To that end, the rates of degradation of the solid phases were computed for each considered environment. Three cement have been studied: CEM I 42.5R/SR, CEM II/A-V 42.5R and CEM IV/B-(P-V) 32.5 N. The pastes have been exposed to five environments: sodium acetate/acetic acid 0.35 M, sodium sulfate solution 0.17 M, a solution representing natural water, saturated calcium hydroxide solution and laboratory environment. The attack mechanism was meant to be unidirectional, in order to achieve so; all sides of cylinders were sealed except from the attacked surface. The cylinders were taking out of the exposition environments after 2, 4, 7, 14, 30, 58 and 90 days. Both aggressive solution variations in solid phases and in different depths have been characterized. To each age and depth the calcium, magnesium and iron contents have been analyzed. Hydrated phases evolution studied, using thermal analysis, and crystalline compound changes, using X ray diffraction have been also analyzed. Sodium sulphate and water solutions stabilize an outer pH near to 8 in short time, however the stability of the most pH dependent phases is not the same. Although having similar pH and existing the possibility of forming a plaster layer near to the calcium leaching surface, this stability is greater than other sulphate solutions. Stability variations of solids formed by inverse diffusion, determine the rate of degradation.

Diffusion of Zn into GaAs and AlGaAs from isothermal Liquid-phase epitaxy solutions

In this work we present results of zinc diffusion in GaAs using the liquid phase epitaxy technique from liquid solutions of Ga‐As‐Zn and Ga‐As‐Al‐Zn. Using silicon‐doped n‐GaAs substrates, working at a diffusion temperature of 850 °C, and introducing a dopant concentration ranging 1018–1019 cm−3, the most important findings regarding the diffusion properties are as follows: (a) zinc concentration in the solid depends on the square root of zinc atomic fraction in the liquid; (b) the diffusion is dominated by the interstitial‐substitutional process; (c) the diffusivity D varies as about C3 in the form D=2.9×10−67C3.05; (d) aluminum plays the role of the catalyst of the diffusion process, if it is introduced in the liquid solution, since it is found that D varies as (γAsXlAs)−1; (e) the zinc interstitial is mainly doubly ionized (Zn++i); (f) the zinc diffusion coefficient in Al0.85 Ga0.15 As is about four times greater than in GaAs; (g) by means of all these results, it is possible to control zinc diffusion processes in order to obtain optimized depth junctions and doping levels in semiconductor device fabrication.

Multiple Input-Output Bidirectional Solid State Transformer Based on a Series Resonant Converter

Las fuentes de alimentación de modo conmutado (SMPS en sus siglas en inglés) se utilizan ampliamente en una gran variedad de aplicaciones. La tarea más difícil para los diseñadores de SMPS consiste en lograr simultáneamente la operación del convertidor con alto rendimiento y alta densidad de energía. El tamaño y el peso de un convertidor de potencia está dominado por los componentes pasivos, ya que estos elementos son normalmente más grandes y más pesados que otros elementos en el circuito. Para una potencia de salida dada, la cantidad de energía almacenada en el convertidor que ha de ser entregada a la carga en cada ciclo de conmutación, es inversamente proporcional a la frecuencia de conmutación del convertidor. Por lo tanto, el aumento de la frecuencia de conmutación se considera un medio para lograr soluciones más compactas con los niveles de densidad de potencia más altos. La importancia de investigar en el rango de alta frecuencia de conmutación radica en todos los beneficios que se pueden lograr: además de la reducción en el tamaño de los componentes pasivos, el aumento de la frecuencia de conmutación puede mejorar significativamente prestaciones dinámicas de convertidores de potencia. Almacenamiento de energía pequeña y el período de conmutación corto conducen a una respuesta transitoria del convertidor más rápida en presencia de las variaciones de la tensión de entrada o de la carga. Las limitaciones más importantes del incremento de la frecuencia de conmutación se relacionan con mayores pérdidas del núcleo magnético convencional, así como las pérdidas de los devanados debido a los efectos pelicular y proximidad. También, un problema potencial es el aumento de los efectos de los elementos parásitos de los componentes magnéticos - inductancia de dispersión y la capacidad entre los devanados - que causan pérdidas adicionales debido a las corrientes no deseadas. Otro factor limitante supone el incremento de las pérdidas de conmutación y el aumento de la influencia de los elementos parásitos (pistas de circuitos impresos, interconexiones y empaquetado) en el comportamiento del circuito. El uso de topologías resonantes puede abordar estos problemas mediante el uso de las técnicas de conmutaciones suaves para reducir las pérdidas de conmutación incorporando los parásitos en los elementos del circuito. Sin embargo, las mejoras de rendimiento se reducen significativamente debido a las corrientes circulantes cuando el convertidor opera fuera de las condiciones de funcionamiento nominales. A medida que la tensión de entrada o la carga cambian las corrientes circulantes incrementan en comparación con aquellos en condiciones de funcionamiento nominales. Se pueden obtener muchos beneficios potenciales de la operación de convertidores resonantes a más alta frecuencia si se emplean en aplicaciones con condiciones de tensión de entrada favorables como las que se encuentran en las arquitecturas de potencia distribuidas. La regulación de la carga y en particular la regulación de la tensión de entrada reducen tanto la densidad de potencia del convertidor como el rendimiento. Debido a la relativamente constante tensión de bus que se encuentra en arquitecturas de potencia distribuidas los convertidores resonantes son adecuados para el uso en convertidores de tipo bus (transformadores cc/cc de estado sólido). En el mercado ya están disponibles productos comerciales de transformadores cc/cc de dos puertos que tienen muy alta densidad de potencia y alto rendimiento se basan en convertidor resonante serie que opera justo en la frecuencia de resonancia y en el orden de los megahercios. Sin embargo, las mejoras futuras en el rendimiento de las arquitecturas de potencia se esperan que vengan del uso de dos o más buses de distribución de baja tensión en vez de una sola. Teniendo eso en cuenta, el objetivo principal de esta tesis es aplicar el concepto del convertidor resonante serie que funciona en su punto óptimo en un nuevo transformador cc/cc bidireccional de puertos múltiples para atender las necesidades futuras de las arquitecturas de potencia. El nuevo transformador cc/cc bidireccional de puertos múltiples se basa en la topología de convertidor resonante serie y reduce a sólo uno el número de componentes magnéticos. Conmutaciones suaves de los interruptores hacen que sea posible la operación en las altas frecuencias de conmutación para alcanzar altas densidades de potencia. Los problemas posibles con respecto a inductancias parásitas se eliminan, ya que se absorben en los Resumen elementos del circuito. El convertidor se caracteriza con una muy buena regulación de la carga propia y cruzada debido a sus pequeñas impedancias de salida intrínsecas. El transformador cc/cc de puertos múltiples opera a una frecuencia de conmutación fija y sin regulación de la tensión de entrada. En esta tesis se analiza de forma teórica y en profundidad el funcionamiento y el diseño de la topología y del transformador, modelándolos en detalle para poder optimizar su diseño. Los resultados experimentales obtenidos se corresponden con gran exactitud a aquellos proporcionados por los modelos. El efecto de los elementos parásitos son críticos y afectan a diferentes aspectos del convertidor, regulación de la tensión de salida, pérdidas de conducción, regulación cruzada, etc. También se obtienen los criterios de diseño para seleccionar los valores de los condensadores de resonancia para lograr diferentes objetivos de diseño, tales como pérdidas de conducción mínimas, la eliminación de la regulación cruzada o conmutación en apagado con corriente cero en plena carga de todos los puentes secundarios. Las conmutaciones en encendido con tensión cero en todos los interruptores se consiguen ajustando el entrehierro para obtener una inductancia magnetizante finita en el transformador. Se propone, además, un cambio en los señales de disparo para conseguir que la operación con conmutaciones en apagado con corriente cero de todos los puentes secundarios sea independiente de la variación de la carga y de las tolerancias de los condensadores resonantes. La viabilidad de la topología propuesta se verifica a través una extensa tarea de simulación y el trabajo experimental. La optimización del diseño del transformador de alta frecuencia también se aborda en este trabajo, ya que es el componente más voluminoso en el convertidor. El impacto de de la duración del tiempo muerto y el tamaño del entrehierro en el rendimiento del convertidor se analizan en un ejemplo de diseño de transformador cc/cc de tres puertos y cientos de vatios de potencia. En la parte final de esta investigación se considera la implementación y el análisis de las prestaciones de un transformador cc/cc de cuatro puertos para una aplicación de muy baja tensión y de decenas de vatios de potencia, y sin requisitos de aislamiento. Abstract Recently, switch mode power supplies (SMPS) have been used in a great variety of applications. The most challenging issue for designers of SMPS is to achieve simultaneously high efficiency operation at high power density. The size and weight of a power converter is dominated by the passive components since these elements are normally larger and heavier than other elements in the circuit. If the output power is constant, the stored amount of energy in the converter which is to be delivered to the load in each switching cycle is inversely proportional to the converter’s switching frequency. Therefore, increasing the switching frequency is considered a mean to achieve more compact solutions at higher power density levels. The importance of investigation in high switching frequency range comes from all the benefits that can be achieved. Besides the reduction in size of passive components, increasing switching frequency can significantly improve dynamic performances of power converters. Small energy storage and short switching period lead to faster transient response of the converter against the input voltage and load variations. The most important limitations for pushing up the switching frequency are related to increased conventional magnetic core loss as well as the winding loss due to the skin and proximity effect. A potential problem is also increased magnetic parasitics – leakage inductance and capacitance between the windings – that cause additional loss due to unwanted currents. Higher switching loss and the increased influence of printed circuit boards, interconnections and packaging on circuit behavior is another limiting factor. Resonant power conversion can address these problems by using soft switching techniques to reduce switching loss incorporating the parasitics into the circuit elements. However the performance gains are significantly reduced due to the circulating currents when the converter operates out of the nominal operating conditions. As the input voltage or the load change the circulating currents become higher comparing to those ones at nominal operating conditions. Multiple Input-Output Many potential gains from operating resonant converters at higher switching frequency can be obtained if they are employed in applications with favorable input voltage conditions such as those found in distributed power architectures. Load and particularly input voltage regulation reduce a converter’s power density and efficiency. Due to a relatively constant bus voltage in distributed power architectures the resonant converters are suitable for bus voltage conversion (dc/dc or solid state transformation). Unregulated two port dc/dc transformer products achieving very high power density and efficiency figures are based on series resonant converter operating just at the resonant frequency and operating in the megahertz range are already available in the market. However, further efficiency improvements of power architectures are expected to come from using two or more separate low voltage distribution buses instead of a single one. The principal objective of this dissertation is to implement the concept of the series resonant converter operating at its optimum point into a novel bidirectional multiple port dc/dc transformer to address the future needs of power architectures. The new multiple port dc/dc transformer is based on a series resonant converter topology and reduces to only one the number of magnetic components. Soft switching commutations make possible high switching frequencies to be adopted and high power densities to be achieved. Possible problems regarding stray inductances are eliminated since they are absorbed into the circuit elements. The converter features very good inherent load and cross regulation due to the small output impedances. The proposed multiple port dc/dc transformer operates at fixed switching frequency without line regulation. Extensive theoretical analysis of the topology and modeling in details are provided in order to compare with the experimental results. The relationships that show how the output voltage regulation and conduction losses are affected by the circuit parasitics are derived. The methods to select the resonant capacitor values to achieve different design goals such as minimum conduction losses, elimination of cross regulation or ZCS operation at full load of all the secondary side bridges are discussed. ZVS turn-on of all the switches is achieved by relying on the finite magnetizing inductance of the Abstract transformer. A change of the driving pattern is proposed to achieve ZCS operation of all the secondary side bridges independent on load variations or resonant capacitor tolerances. The feasibility of the proposed topology is verified through extensive simulation and experimental work. The optimization of the high frequency transformer design is also addressed in this work since it is the most bulky component in the converter. The impact of dead time interval and the gap size on the overall converter efficiency is analyzed on the design example of the three port dc/dc transformer of several hundreds of watts of the output power for high voltage applications. The final part of this research considers the implementation and performance analysis of the four port dc/dc transformer in a low voltage application of tens of watts of the output power and without isolation requirements.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Factors impacting the market share of Construction and Demolition (C&D) Waste recycling solutions

Current EU Directives force the Member States to assure by 2020 that 70% of the Construction and Demolition (C&D) waste is recovered instead of landfilled. While some countries have largely achieved this target, others still have a long way to go. For better understanding the differences arising from local disparities, six factors related to technical, economic, legislative and environmental aspects have been identified as crucial influences in the market share of C&D waste recycling solutions. These factors are able to identify the causes that limit the recycling rate of a certain region. Moreover, progress towards an efficient waste management can vary through the improvement of a single factor. This study provides the background for further fine-tuning the factors and their combination into a mathematical model for assessing the market share of C&D recycling solutions.