Magnetic losses evolution of a semi-processed steel during forced aging treatments

An ultra-low carbon steel (30 ppm after decarburization) containing Al and Si was aged for distinct soaking times at 210 degrees C. The core loss increased continuously until around 24 h. After that, only slight changes were verified. It was found that only the hysteresis loss component changed during the aging treatment. By internal friction test and transmission electron microscopy it was seen that carbon precipitation caused the magnetic aging. By scanning electron microscopy it could be concluded that the increase of aging index was attributed to the high number of carbides larger than 0.1 mu m. (C) 2008 Elsevier B. V. All rights reserved.

Magnetic loss, permeability dispersion, and role of eddy currents in Mn-Zn sintered ferrites

Magnetic energy losses and permeability have been investigated in laboratory prepared and commercial Mn-Zn sintered ferrites from quasi-static conditions up to 10 MHz. The mechanisms leading to energy dissipation, either due to domain wall displacements or magnetization rotations, have been quantitatively assessed and their respective roles have been clarified. Domain wall processes dissipate energy by pure relaxation effects, while rotations display resonant absorption of energy over a broad range of frequencies. Their specific contributions to the permeability and its frequency dispersion are thus identified and separately evaluated. It is shown that eddy currents are always too weak to appreciably contribute to the losses over the whole investigated frequency range and that rotations are the dominant magnetization and loss producing mechanisms on approaching the MHz range, as predicted by the Landau-Lifshitz-Gilbert equation with distributed anisotropy fields. (C) 2008 Elsevier B.V. All rights reserved.

Effect of rolling on the residual stresses and magnetic properties of a 0.5% Si electrical steel

Cold-rolled (0-19% of reduction) 0.5% Si electrical steel sheets were studied in detail, including macro and micro residual stress measurements, crystallographic texture, dc-hysteresis curves and iron losses. Even for the smallest deformation, losses increase significantly, with large increase of the hysteresis losses, whereas the anomalous losses reduce slightly. The residual microstresses are similar to 150-350 MPa, whereas residual macrostresses are compressive, similar to 50 MPa. The large increase of the hysteresis losses is attributed to the residual microstresses. The dislocation density estimated by X-ray diffraction is in reasonable agreement with that predicted from the Sablik et al. model for effect of plastic deformation on hysteresis. The intensity of the texture fibers {1 1 1}< u v w > and < 110 >//RD (RD = rolling direction) increases with the reduction. (C) 2008 Elsevier B.V. All rights reserved.

The influence of different voltage waveforms and grain sizes in electrical steels losses

Square and two-level pulse width modulation (PWM) magnetic induction waveforms are investigated and their effect on electrical steels losses as a function of the grain size is determined. The increase of hysteresis losses-as compared to that resulting from sinusoidal voltages-occurs only for two-level PWM waveforms. Total losses are lower for square waveform, and the difference between losses under square and sinusoidal waveform increase with increasing grain size, result explained with the loss separation model. (C) 2008 Elsevier B.V. All rights reserved.

Effect of Ti and C additions on structural and magnetic properties of (Pr,Nd)-Fe-B nanocrystalline magnetic materials

Effects of titanium carbide (TiC) addition on structural and magnetic properties of isotropic (Pr,Nd)-Fe-B nanocrystalline magnetic materials have been investigated. In this work, we investigate the effect of TiC addition on a (Pr,Nd)-poor and B-rich composition, as well as on a B-poor and (Nd, Pr)-rich composition. Rapidly solidified (Pr, Nd)-Fe-B alloys were prepared by melt-spinning. The compositions studied were (Pr(1-x)Nd(x))(4)Fe(78)B(18) (x = 0, 0.5, and 1) with addition of 3 at% TiC. Unlike the (Pr(x)Nd(1-x))(9.5)Fe(84.5)B(6) materials that present excellent values for coercive. field and energy product, the (Pr,Nd)-poor and B-rich composition alloys with TiC addition present lower values. Rietveld analysis of X-ray data and Mossbauer spectroscopy revealed that samples are predominantly composed of Fe(3)B and alpha-Fe. For the RE-rich compositions (Pr(x)Nd(1-x))(9.5)Fe(84.5)B(6) (x = 0.1, 0.25, 0.5, 0.75, and 1) with the addition of 3 at% TiC, the highest coercive field and energy product (8.4 kOe and 14.4 MGOe, respectively) were obtained for the composition Pr(9.5)Fe(84.5)B(6). (c) 2008 Elsevier B.V. All rights reserved.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Open-circuit voltages: Theoretical and experimental optimizations of rear passivated silicon solar cells using Fz and Cz wafers

The theoretical and experimental open-circuit voltage optimizations of a simple fabrication process of silicon solar cells n(+)p with rear passivation are presented. The theoretical results were obtained by using an in-house developed program, including the light trapping effect and metal-grid optimization. On the other hand, the experimental steps were monitored by the photoconductive decay technique. The starting materials presented thickness of about 300 pm and resistivities: FZ (0.5 Omega cm), Cz-type 1 (2.5 Omega cm) and Cz-type 2 (3.3 Omega cm). The Gaussian profile emitters were optimized with sheet resistance between 55 Omega/sq and 100 Omega/sq, and approximately 2.0 mu m thickness in accordance to the theoretical results. Excellent implied open-circuit voltages of 670.8 mV, 652.5 mV and 662.6 mV, for FZ, Cz-type 1 and Cz-type 2 silicon wafers, respectively, could be associated to the measured lifetimes that represents solar cell efficiency up to 20% if a low cost anti-reflection coating system, composed by random pyramids and SiO(2) layer, is considered even for typical Cz silicon. (C) 2009 Elsevier Ltd. All rights reserved.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Probing Individual Quantum Dots: Noise in Self-Assembled Systems

In this work we explore the noise characteristics in lithographically-defined two terminal devices containing self-assembled InAs/InP quantum dots. The experimental ensemble of InAs dots show random telegraph noise (RTN) with tuneable relative amplitude-up to 150%-in well defined temperature and source-drain applied voltage ranges. Our numerical simulation indicates that the RTN signature correlates with a very low number of quantum dots acting as effective charge storage centres in the structure for a given applied voltage. The modulation in relative amplitude variation can thus be associated to the altered electrostatic potential profile around such centres and enhanced carrier scattering provided by a charged dot.

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO(x)) dielectric layer, deposited with different oxygen partial pressure (30,35 and 40%) and annealed at 550, 750 and 1000 degrees C, were fabricated and characterized. Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of - 1 V, as low as 1 nA/cm(2) for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers. (C) 2009 Elsevier B.V. All rights reserved.

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.