Optical learning in a smart spatial light modulator

A synaptic plane rendered by an array of smart pixels was described regarding its application as a complementary component for neural network implementation. The smart spatial light modulator featured auto-modification abilities. Thus, an optical system incorporating this device can show self-reliant optical learning. Furthermore, the optical system design, in the area of its optical interconnection scheme, is highly flexible since the independent weight-plane pixels eliminated the difficulty between weight update calculation and weight representation.

Smart chemical sensor application of ZnO nanowires grown on CMOS compatible SOI microheater platform

Smart chemical sensor based on CMOS(complementary metal-oxide- semiconductor) compatible SOI(silicon on insulator) microheater platform was realized by facilitating ZnO nanowires growth on the small membrane at the relatively low temperature. Our SOI microheater platform can be operated at the very low power consumption with novel metal oxide sensing materials, like ZnO or SnO2 nanostructured materials which demand relatively high sensing temperature. In addition, our sol-gel growth method of ZnO nanowires on the SOI membrane was found to be very effective compared with ink-jetting or CVD growth techniques. These combined techniques give us the possibility of smart chemical sensor technology easily merged into the conventional semiconductor IC application. The physical properties of ZnO nanowire network grown by the solution-based method and its chemical sensing property also were reported in this paper.

700V smart trench IGBT with monolithic over-voltage and over-current protecting functions

An advanced 700V Smart Trench IGBT with monolithically integrated over-voltage and over-current protecting circuits is presented in this paper. The proposed Smart IGBT comprises a sense IGBT, a low voltage lateral n-channel MOSFET (M 1), an avalanche diode (D av), and poly-crystalline Zener diodes (ZD) and resistor (R poly). Mix-mode transient simulations with MEDICI have proven the functionalities of the protecting circuits when the device is operating under abnormal conditions, such as Unclamped Inductive Switching (UIS) and Short Circuit (SC) condition. A Trench IGBT process is used to fabricate this device with total 11 masks including one metal mask only. The characterizations of the fabricated device exhibit the clamping capability of the avalanche diode and voltage pull-down ability of the MOSFET. © 2012 IEEE.

ℓasso MPC: Smart regulation of over-actuated systems

In this paper, a novel MPC strategy is proposed, and referred to as asso MPC. The new paradigm features an 1-regularised least squares loss function, in which the control error variance competes with the sum of input channels magnitude (or slew rate) over the whole horizon length. This cost choice is motivated by the successful development of LASSO theory in signal processing and machine learning. In the latter fields, sum-of-norms regularisation have shown a strong capability to provide robust and sparse solutions for system identification and feature selection. In this paper, a discrete-time dual-mode asso MPC is formulated, and its stability is proven by application of standard MPC arguments. The controller is then tested for the problem of ship course keeping and roll reduction with rudder and fins, in a directional stochastic sea. Simulations show the asso MPC to inherit positive features from its corresponding regressor: extreme reduction of decision variables' magnitude, namely, actuators' magnitude (or variations), with a finite energy error, being particularly promising for over-actuated systems. © 2012 AACC American Automatic Control Council).

An integrated service-device-technology roadmap for smart city development

Firms and other organizations use Technology Roadmapping (TRM) extensively as a framework for supporting research and development of future technologies and products that could sustain a competitive advantage. While the importance of technology strategy has received more attention in recent years, few research studies have examined how roadmapping processes are used to explore the potential convergence of products and services that may be developed in the future. The aim of this paper is to introduce an integrated roadmapping process for services, devices and technologies capable of implementing a smart city development R&D project in Korea. The paper applies a QFD (Quality Function Deployment) method to establish interconnections between services and devices, and between devices and technologies. The method is illustrated by a detailed case study, which shows how different types of roadmap can be coordinated with each other to produce a clear representation of the technological changes and uncertainties associated with the strategic planning of complex innovations. © 2012 Elsevier Inc.

Active control of normal shock wave/turbulent boundary layer interaction using "Smart" piezoelectric flap actuators

This paper looks at active control of the normal shock wave/turbulent boundary layer interaction (SBLI) using smart flap actuators. The actuators are manufactured by bonding piezoelectric material to an inert substrate to control the bleed/suction rate through a plenum chamber. The cavity provides communication of signals across the shock, allowing rapid thickening of the boundary layer approaching the shock, which splits into a series of weaker shocks forming a lambda shock foot, reducing wave drag. Active control allows optimum control of the interaction, as it would be capable of positioning the control region around the original shock position and control the rate of mass transfer. © 2004 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.