Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

Thesis (Master's)--University of Washington, 2016-06

Synthesis of Silver Nanoparticle Based Conductive Inks for Additively Manufactured Electronics

Thesis (Master's)--University of Washington, 2016-06

A heuristic approach for component scheduling on a high-speed PCB assembly machine

The collect-and-place machine is one of the most widely used placement machines for assembling electronic components on the printed circuit boards (PCBs). Nevertheless, the number of researches concerning the optimisation of the machine performance is very few. This motivates us to study the component scheduling problem for this type of machine with the objective of minimising the total assembly time. The component scheduling problem is an integration of the component sequencing problem, that is, the sequencing of component placements; and the feeder arrangement problem, that is, the assignment of component types to feeders. To solve the component scheduling problem efficiently, a hybrid genetic algorithm is developed in this paper. A numerical example is used to compare the performance of the algorithm with different component grouping approaches and different population sizes.

Effect of pulsed current on the electrodeposition of chromium and copper

This research was concerned with the effects of pulsed current on the electrodeposition of chromium and copper. In the case of the latter metal, a novel application has been studied and a theory proposed for the ability to improve throwing power by the joint use of organic additives and pulsed reverse current. During the course of the research, several improvements were made to the pulse plating unit.Chromium. A study was made of the effect of square wave pulsed current on various physical properties of deposits from three hard chromium plating electrolytes. The effect of varying frequency at a duty cycle of 50% on the mean bulk internal stress, visual appearance, hardness, crack characteristics and surface topography of the electrodeposits was determined. X-ray diffraction techniques were used to study the phases present in the deposits. The effect of varying frequency on the cathodic efficiencies of the electrolytes was also determined. It was found that pulsed current reduced the internal stress of deposits from the sulphate catalysed electrolyte. It also reduced or eliminated cracking of deposits and reduced deposit brightness. Under certain conditions, pulsed current was found to induce the co-deposition of hydrides of chromium. Deposit hardness was found to be reduced by the use of pulsed current. Cathodic efficiencies of the high efficiency electrolytes were reduced by use of pulsed current although this effect was minimised at high frequencies. The sulphate catalysed electrolyte showed an increase in efficiency over the frequency range where hydrides were co-deposited.Copper. The polarisation behaviour of acid copper solutions containing polyethers, sulphopropyl sulphides and chloride ions was studied using both direct and pulse reverse current. The effect of these additives on the rest potentials of copper deposits immersed in the electrolyte was also studied. Hole Throwing Power on printed circuit boards was determined using a specially designed test cell. The effect of pulsed reverse current on the hole throwing power of commercially produced printed circuit boards was also studied. Polyethers were found to have an inhibiting effect on the deposition of copper whereas the sulphopropyl sulphides produced a stimulating (i.e. depolarising) effect. Studies of rest potentials made when both additives were present indicated that the sulphopropyl sulphide was preferentially adsorbed. The use of pulsed reverse current in solutions containing both polyether and sulphopropyl sulphide was found to cause desorption of the sulphopropyl sulphide at the cathode surface. Thus, at higher current densities, the inhibiting effect of the polyether produced an increase in the cathodic polarisation potential. At lower current densities, the depolarisation effect of the sulphopropyl sulphide could still occur. On printed circuit boards, this effect was found to produce an increase in the `hole throwing power' due to depolarisation of the holes relative to the surface of the boards. Typically, using direct current, hole/surface thickness ratios of 40% were obtained when plating 0.6 mm holes in a 3.2 mm thick board at a current density of 3 A/dm2 whereas using pulsed reverse current, ratios of 80% could be obtained at an equivalent rate of deposition. This was observed both in laboratory tests and on commercially plated boards.

Polypropylene as a reductive agent for dehalogenation of brominated organic compounds

A new method for debromination of organics by a reductive medium like polypropylene is investigated. The reaction is carried out in inert atmosphere to avoid rapid oxidation of the polymer. Through this detoxification procedure, hydrogen bromide and small brominated alkanes are formed. Experiments in closed ampoules are carried out with tetrabromobisphenol A, dibromophenol, pentabromodiphenyl ether, dichlorophenol and an oil formed by pyrolysis of printed circuit boards in the Haloclean® process. The reaction is examined under isothermal conditions in a temperature range between 300 and 400°C and a residence time between 10 and 30 min. Optimal conditions were found at 350°C and at a residence time of 20 min. As chlorinated phenols are not destroyed under these conditions, the process may be a valuable procedure to gain hydrogen bromide out of mixtures of halogenated feed materials. Also, under atmospheric pressure, a reaction between polypropylene and brominated compounds takes place as could be proved by thermogravimetric analysis. Bromobenzene has an accelerating effect on the rate of weight loss of the polymer, but at higher concentrations, it can also be slowed down. © 2003 Elsevier Ltd. All rights reserved.

Characterization of ultra wideband antennas for personal communication devices using finite difference time domain technique

The current mobile networks don't offer sufficient data rates to support multimedia intensive applications in development for multifunctional mobile devices. Ultra wideband (UWB) wireless technology is being considered as the solution to overcome data rate bottlenecks in the current mobile networks. UWB is able to achieve such high data transmission rates because it transmits data over a very large chunk of the frequency spectrum. As currently approved by the U.S. Federal Communication Commission it utilizes 7.5 GHz of spectrum between 3.1 GHz and 10.6 GHz. ^ Successful transmission and reception of information data using UWB wireless technology in mobile devices, requires an antenna that has linear phase, low dispersion and a voltage standing wave ratio (VSWR) ≤ 2 throughout the entire frequency band. Compatibility with an integrated circuit requires an unobtrusive and electrically small design. The previous techniques that have been used to optimize the performance of UWB wireless systems, involve proper design of source pulses for optimal UWB performance. The goal of this work is directed towards the designing of antennas for personal communication devices, with optimal UWB bandwidth performance. Several techniques are proposed for optimal UWB bandwidth performance of the UWB antenna designs in this Ph.D. dissertation. ^ This Ph.D. dissertation presents novel UWB antenna designs for personal communication devices that have been characterized and optimized using the finite difference time domain (FDTD) technique. The antenna designs reported in this research are physically compact, planar for low profile use, with sufficient impedance bandwidth (>20%), antenna input impedance of 50-Ω, and an omni-directional (±1.5 dB) radiation pattern in the operating bandwidth. ^

VLSI testing and characterization system for micro electro-mechanical (MEM) sensors

The purpose of this investigation was to develop and implement a general purpose VLSI (Very Large Scale Integration) Test Module based on a FPGA (Field Programmable Gate Array) system to verify the mechanical behavior and performance of MEM sensors, with associated corrective capabilities; and to make use of the evolving System-C, a new open-source HDL (Hardware Description Language), for the design of the FPGA functional units. System-C is becoming widely accepted as a platform for modeling, simulating and implementing systems consisting of both hardware and software components. In this investigation, a Dual-Axis Accelerometer (ADXL202E) and a Temperature Sensor (TMP03) were used for the test module verification. Results of the test module measurement were analyzed for repeatability and reliability, and then compared to the sensor datasheet. Further study ideas were identified based on the study and results analysis. ASIC (Application Specific Integrated Circuit) design concepts were also being pursued.

System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

A heuristic algorithm to generate test program sequences for moving probe electronic test equipment

The electronics industry, is experiencing two trends one of which is the drive towards miniaturization of electronic products. The in-circuit testing predominantly used for continuity testing of printed circuit boards (PCB) can no longer meet the demands of smaller size circuits. This has lead to the development of moving probe testing equipment. Moving Probe Test opens up the opportunity to test PCBs where the test points are on a small pitch (distance between points). However, since the test uses probes that move sequentially to perform the test, the total test time is much greater than traditional in-circuit test. While significant effort has concentrated on the equipment design and development, little work has examined algorithms for efficient test sequencing. The test sequence has the greatest impact on total test time, which will determine the production cycle time of the product. Minimizing total test time is a NP-hard problem similar to the traveling salesman problem, except with two traveling salesmen that must coordinate their movements. The main goal of this thesis was to develop a heuristic algorithm to minimize the Flying Probe test time and evaluate the algorithm against a "Nearest Neighbor" algorithm. The algorithm was implemented with Visual Basic and MS Access database. The algorithm was evaluated with actual PCB test data taken from Industry. A statistical analysis with 95% C.C. was performed to test the hypothesis that the proposed algorithm finds a sequence which has a total test time less than the total test time found by the "Nearest Neighbor" approach. Findings demonstrated that the proposed heuristic algorithm reduces the total test time of the test and, therefore, production cycle time can be reduced through proper sequencing.

Especificações e concepções de front-end UHF integrado e multipadrão em tecnologia CMOS 130nm

The Brazilian Environmental Data Collecting System (SBCDA) collects and broadcasts meteorological and environmental data, to be handled by dozens of institutions and organizations. The system space segment, composed by the data collecting satellites, plays an important role for the system operation. To ensure the continuity and quality of these services, efforts are being made to the development of new satellite architectures. Aiming a reduction of size and power consumption, the design of an integrated circuit containing a receiver front-end is proposed, to be embedded in the next SBCDA satellite generations. The circuit will also operate under the requirements of the international data collecting standard ARGOS. This work focuses on the design of an UHF low noise amplifier and mixers in a CMOS standard technology. The specifi- cations are firstly described and the circuit topologies presented. Then the circuit conception is discussed and the design variables derived. Finally, the layout is designed and the final results are commented. The chip will be fabricated in a 130 nm technology from ST Microelectronics.

Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA

This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Amplificador integrador com ganho programável por largura de pulso

This work deals with the research and development of a Pulse Width Programmable Gain Integrating Amplifier. Two Pulse Width Programmable Gain Amplifier architectures are proposed, one based on discrete components and another based on switched capacitors. From the operating requirements defined for the study, parameters are defined and simulations are carried out to validate the architecture. Subsequently, the circuit and the software are developed and tested. It is performed the evaluation of the circuits regarding the two proposed architectures, and from that, an architecture is selected to be improved, aiming the development of an integrated circuit in a future work.

Mecanismo de tolerância a falhas através de escalonamento para uma arquitetura reconfigurável de grão grosso

The continuous evolution of integrated circuit technology has allowed integrating thousands of transistors on a single chip. This is due to the miniaturization process, which reduces the diameter of wires and transistors. One drawback of this process is that the circuit becomes more fragile and susceptible to break, making the circuit more susceptible to permanent faults during the manufacturing process as well as during their lifetime. Coarse Grained Reconfigurable Architectures (CGRAs) have been used as an alternative to traditional architectures in an attempt to tolerate such faults due to its intrinsic hardware redundancy and high performance. This work proposes a fault tolerance mechanism in a CGRA in order to increase the architecture fault tolerance even considering a high fault rate. The proposed mechanism was added to the scheduler, which is the mechanism responsible for mapping instructions onto the architecture. The instruction mapping occurs at runtime, translating binary code without the need for recompilation. Furthermore, to allow faster implementation, instruction mapping is performed using a greedy module scheduling algorithm, which consists of a software pipeline technique for loop acceleration. The results show that, even with the proposed mechanism, the time for mapping instructions is still in order of microseconds. This result allows that instruction mapping process remains at runtime. In addition, a study was also carried out mapping scheduler rate. The results demonstrate that even at fault rates over 50% in functional units and interconnection components, the scheduler was able to map instructions onto the architecture in most of the tested applications.

Caracterização e separação física de placas de circuito impresso de computadores obsoletos

The unbridled consumption of electronic equipment associated with fast immersion of new technologies on the market leads to the accelerated growth of electronic waste. Such waste mostly contains printed circuit boards in its structure. Printed circuit boards have many metals, including heavy metals, being highly toxic. Electronic waste is discarded improperly and indiscriminately, usually without any previous treatment and with other municipal waste, contaminating the environment and causing serious problems to human health. Beyond these metals, there are also precious metals and high value-added basis, that can be recovered and recycled, reducing the exploration of natural resources. Thus, due to the high growth potential and reuse of these waste treatment processes, characterization and separation were applied to the printed circuit boards. The printed circuit boards were subjected to physical treatments such as dismantling, crushing, sizing separation, magnetic separation and chemical treatments such as pyrolysis and leaching. Through characterization process (pyrolysis and leaching) the proportions of the components of the granulometric range were determined: 46,08% of metals; 23,32% of polymers and 30,60% of ceramics. It was also observed by particle size separation that metal components tend to concentrate in coarse fractions, while polymeric and ceramic components in fine fractions. From the magnetic separation process was obtained 12,08% of magnetic material and 82,33% of non-magnetic material.

Advanced thermal analysis of microelectronics using spreading resistance models

Thermal analysis of electronic devices is one of the most important steps for designing of modern devices. Precise thermal analysis is essential for designing an effective thermal management system of modern electronic devices such as batteries, LEDs, microelectronics, ICs, circuit boards, semiconductors and heat spreaders. For having a precise thermal analysis, the temperature profile and thermal spreading resistance of the device should be calculated by considering the geometry, property and boundary conditions. Thermal spreading resistance occurs when heat enters through a portion of a surface and flows by conduction. It is the primary source of thermal resistance when heat flows from a tiny heat source to a thin and wide heat spreader. In this thesis, analytical models for modeling the temperature behavior and thermal resistance in some common geometries of microelectronic devices such as heat channels and heat tubes are investigated. Different boundary conditions for the system are considered. Along the source plane, a combination of discretely specified heat flux, specified temperatures and adiabatic condition are studied. Along the walls of the system, adiabatic or convective cooling boundary conditions are assumed. Along the sink plane, convective cooling with constant or variable heat transfer coefficient are considered. Also, the effect of orthotropic properties is discussed. This thesis contains nine chapters. Chapter one is the introduction and shows the concepts of thermal spreading resistance besides the originality and importance of the work. Chapter two reviews the literatures on the thermal spreading resistance in the past fifty years with a focus on the recent advances. In chapters three and four, thermal resistance of a twodimensional flux channel with non-uniform convection coefficient in the heat sink plane is studied. The non-uniform convection is modeled by using two functions than can simulate a wide variety of different heat sink configurations. In chapter five, a non-symmetrical flux channel with different heat transfer coefficient along the right and left edges and sink plane is analytically modeled. Due to the edge cooling and non-symmetry, the eigenvalues of the system are defined using the heat transfer coefficient on both edges and for satisfying the orthogonality condition, a normalized function is calculated. In chapter six, thermal behavior of two-dimensional rectangular flux channel with arbitrary boundary conditions on the source plane is presented. The boundary condition along the source plane can be a combination of the first kind boundary condition (Dirichlet or prescribed temperature) and the second kind boundary condition (Neumann or prescribed heat flux). The proposed solution can be used for modeling the flux channels with numerous different source plane boundary conditions without any limitations in the number and position of heat sources. In chapter seven, temperature profile of a circular flux tube with discretely specified boundary conditions along the source plane is presented. Also, the effect of orthotropic properties are discussed. In chapter 8, a three-dimensional rectangular flux channel with a non-uniform heat convection along the heat sink plane is analytically modeled. In chapter nine, a summary of the achievements is presented and some systems are proposed for the future studies. It is worth mentioning that all the models and case studies in the thesis are compared with the Finite Element Method (FEM).