Estudo da compatibilidade eletromagnética em placa de circuito impresso de centrais telefônicas

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Proposta de implementação de redes de base radial em tecnologias CMOS e BiCMOS

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Análise teórica de novos circuladores de 3-portas em cristais fotônicos bidimensionais

Este trabalho apresenta um estudo teórico sobre novos circuladores compactos com 3-portas tipos W e Y, baseados em cristais fotônicos bidimensionais. No circulador tipo Y, os guias de onda que o compõem formam ângulos de 120° entre si (com formato assemelhado ao da letra Y). O circulador tipo W é uma modificação do tipo Y, obtido a partir do reposicionamento de uma das portas entre as outras duas com um ângulo de 60° entre os guias de onda (com formato assemelhado ao da letra W). Os parâmetros geométricos dos cristais foram obtidos dos diagramas de bandas proibidas. O circulador de três portas tipo Y, projetado para operar em frequências de micro-ondas, foi investigado com o objetivo de gerar um protótipo inédito, enquanto que o tipo W, para frequências ópticas, foi investigado para demonstrar a possibilidade de desenvolver um circulador mais compacto em comparação com o tipo Y conhecido. O tipo W pode ser também uma alternativa geométrica mais adequada no design de circuitos integrados. Os modelos são bons no sentido em que possuem elevada isolação (maior que -20 dB em ambos os circuladores) e baixa perda de inserção (maior que -0,5 dB no caso do circulador tipo Y). O circulador tipo W apresenta uma largura de banda de operação em torno de 100 GHz para um nível de -20 dB de isolação, centrado no comprimento de onda de 1,5um. As simulações foram feitas utilizando-se o software comercial COMSOL Multiphysics, o qual se baseia no método dos elementos finitos.

Metodologia de simulação numérica do comportamento térmico em equipamentos eletroeletrônicos

Pós-graduação em Engenharia Elétrica - FEIS

Architectures, stability and optimization for clock distribution networks

Synchronous telecommunication networks, distributed control systems and integrated circuits have its accuracy of operation dependent on the existence of a reliable time basis signal extracted from the line data stream and acquirable to each node. In this sense, the existence of a sub-network (inside the main network) dedicated to the distribution of the clock signals is crucially important. There are different solutions for the architecture of the time distribution sub-network and choosing one of them depends on cost, precision, reliability and operational security. In this work we expose: (i) the possible time distribution networks and their usual topologies and arrangements. (ii) How parameters of the network nodes can affect the reachability and stability of the synchronous state of a network. (iii) Optimizations methods for synchronous networks which can provide low cost architectures with operational precision, reliability and security. (C) 2011 Elsevier B. V. All rights reserved.

Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs

The study of ionizing radiation effects on semiconductor devices is of great relevance for the global technological development and is a necessity in some strategic areas in Brazil. This work presents preliminary results of radiation effects in MOSFETs that were exposed to 3.2 Grad radiation dose produced by a 2.6-MeV proton beam. The focus of this work was to electrically characterize a Rectangular-Gate MOSFET (RGT) and a Circular-Gate MOSFET (CGT), manufactured with the On Semiconductor 0.5 mu m standard CMOS fabrication process and to verify a suitable geometry for space applications. During the experiment, I-DS x V-GS curves were measured. After irradiation, the RGT off-state current (I-OFF) increased approximately two orders of magnitude reaching practically the same value of the I-OFF in the CGT, which only doubled its value. (C) 2011 Elsevier B.V. All rights reserved.

Performance of electronic devices submitted to X-rays and high energy proton beams

In this work we have studied the radiation effects on MOSFET electronic devices. The integrated circuits were exposed to 10 key X-ray radiation and 2.6 MeV energy proton beam. We have irradiated MOSFET devices with two different geometries: rectangular-gate transistor and circular-gate transistor. We have observed the cumulative dose provokes shifts on the threshold voltage and increases or decreases the transistor's off-state and leakage current. The position of the trapped charges in modern CMOS technology devices depends on radiation type, dose rate, total dose, applied bias and is a function of device geometry. We concluded the circular-gate transistor is more tolerant to radiation than the rectangular-gate transistor. (C) 2011 Elsevier B.V. All rights reserved.

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M(2)AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 well-known benchmarks, including random and real applications, and combines up to 8 applications at the same SoC. The experimental results showed that the M(2)AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach.

Analog circuit synthesis performing fast Pareto frontier exploration and analysis through 3D graphs

This paper presents a technique for performing analog design synthesis at circuit level providing feedback to the designer through the exploration of the Pareto frontier. A modified simulated annealing which is able to perform crossover with past anchor points when a local minimum is found which is used as the optimization algorithm on the initial synthesis procedure. After all specifications are met, the algorithm searches for the extreme points of the Pareto frontier in order to obtain a non-exhaustive exploration of the Pareto front. Finally, multi-objective particle swarm optimization is used to spread the results and to find a more accurate frontier. Piecewise linear functions are used as single-objective cost functions to produce a smooth and equal convergence of all measurements to the desired specifications during the composition of the aggregate objective function. To verify the presented technique two circuits were designed, which are: a Miller amplifier with 96 dB Voltage gain, 15.48 MHz unity gain frequency, slew rate of 19.2 V/mu s with a current supply of 385.15 mu A, and a complementary folded cascode with 104.25 dB Voltage gain, 18.15 MHz of unity gain frequency and a slew rate of 13.370 MV/mu s. These circuits were synthesized using a 0.35 mu m technology. The results show that the method provides a fast approach for good solutions using the modified SA and further good Pareto front exploration through its connection to the particle swarm optimization algorithm.

LALP: a language to program custom FPGA-based acceleration engines

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

Spin Orbit Effects in the Electronic Transport Properties of Adsorbed Graphene Nanoribbons

Graphene has received great attention due to its exceptional properties, which include corners with zero effective mass, extremely large mobilities, this could render it the new template for the next generation of electronic devices. Furthermore it has weak spin orbit interaction because of the low atomic number of carbon atom in turn results in long spin coherence lengths. Therefore, graphene is also a promising material for future applications in spintronic devices - the use of electronic spin degrees of freedom instead of the electron charge. Graphene can be engineered to form a number of different structures. In particular, by appropriately cutting it one can obtain 1-D system -with only a few nanometers in width - known as graphene nanoribbon, which strongly owe their properties to the width of the ribbons and to the atomic structure along the edges. Those GNR-based systems have been shown to have great potential applications specially as connectors for integrated circuits. Impurities and defects might play an important role to the coherence of these systems. In particular, the presence of transition metal atoms can lead to significant spin-flip processes of conduction electrons. Understanding this effect is of utmost importance for spintronics applied design. In this work, we focus on electronic transport properties of armchair graphene nanoribbons with adsorbed transition metal atoms as impurities and taking into account the spin-orbit effect. Our calculations were performed using a combination of density functional theory and non-equilibrium Greens functions. Also, employing a recursive method we consider a large number of impurities randomly distributed along the nanoribbon in order to infer, for different concentrations of defects, the spin-coherence length.

TCAD approaches to multidimensional simulation of advanced semiconductor devices

Technology scaling increasingly emphasizes complexity and non-ideality of the electrical behavior of semiconductor devices and boosts interest on alternatives to the conventional planar MOSFET architecture. TCAD simulation tools are fundamental to the analysis and development of new technology generations. However, the increasing device complexity is reflected in an augmented dimensionality of the problems to be solved. The trade-off between accuracy and computational cost of the simulation is especially influenced by domain discretization: mesh generation is therefore one of the most critical steps and automatic approaches are sought. Moreover, the problem size is further increased by process variations, calling for a statistical representation of the single device through an ensemble of microscopically different instances. The aim of this thesis is to present multi-disciplinary approaches to handle this increasing problem dimensionality in a numerical simulation perspective. The topic of mesh generation is tackled by presenting a new Wavelet-based Adaptive Method (WAM) for the automatic refinement of 2D and 3D domain discretizations. Multiresolution techniques and efficient signal processing algorithms are exploited to increase grid resolution in the domain regions where relevant physical phenomena take place. Moreover, the grid is dynamically adapted to follow solution changes produced by bias variations and quality criteria are imposed on the produced meshes. The further dimensionality increase due to variability in extremely scaled devices is considered with reference to two increasingly critical phenomena, namely line-edge roughness (LER) and random dopant fluctuations (RD). The impact of such phenomena on FinFET devices, which represent a promising alternative to planar CMOS technology, is estimated through 2D and 3D TCAD simulations and statistical tools, taking into account matching performance of single devices as well as basic circuit blocks such as SRAMs. Several process options are compared, including resist- and spacer-defined fin patterning as well as different doping profile definitions. Combining statistical simulations with experimental data, potentialities and shortcomings of the FinFET architecture are analyzed and useful design guidelines are provided, which boost feasibility of this technology for mainstream applications in sub-45 nm generation integrated circuits.

Characterization and modeling of low-frequency noise in MOSFETs

For many years, RF and analog integrated circuits have been mainly developed using bipolar and compound semiconductor technologies due to their better performance. In the last years, the advance made in CMOS technology allowed analog and RF circuits to be built with such a technology, but the use of CMOS technology in RF application instead of bipolar technology has brought more issues in terms of noise. The noise cannot be completely eliminated and will therefore ultimately limit the accuracy of measurements and set a lower limit on how small signals can be detected and processed in an electronic circuit. One kind of noise which affects MOS transistors much more than bipolar ones is the low-frequency noise. In MOSFETs, low-frequency noise is mainly of two kinds: flicker or 1/f noise and random telegraph signal noise (RTS). The objective of this thesis is to characterize and to model the low-frequency noise by studying RTS and flicker noise under both constant and switched bias conditions. The effect of different biasing schemes on both RTS and flicker noise in time and frequency domain has been investigated.

Modelli Digitali e Archivi di Progetto. Sistemi integrati di documentazione per l'architettura.

Le tecniche dell'informazione e i metodi della comunicazione hanno modificato il modo di redigere documenti destinati a trasmettere la conoscenza, in un processo che è a tutt'oggi in corso di evoluzione. Anche l'attività progettuale in ingegneria ed architettura, pure in un settore caratterizzato da una notevole inerzia metodologica e restio all'innovazione quale è quello dell'industria edilizia, ha conosciuto profonde trasformazioni in ragione delle nuove espressioni tecnologiche. Da tempo l'informazione necessaria per realizzare un edificio, dai disegni che lo rappresentano sino ai documenti che ne indicano le modalità costruttive, può essere gestita in maniera centralizzata mediante un unico archivio di progetto denominato IPDB (Integrated Project DataBase) pur essendone stata recentemente introdotta sul mercato una variante più operativa chiamata BIM (Building Information Modelling). Tuttavia l'industrializzazione del progetto che questi strumenti esplicano non rende conto appieno di tutti gli aspetti che vedono la realizzazione dell'opera architettonica come collettore di conoscenze proprie di una cultura progettuale che, particolarmente in Italia, è radicata nel tempo. La semantica della rappresentazione digitale è volta alla perequazione degli elementi costitutivi del progetto con l'obiettivo di catalogarne le sole caratteristiche fabbricative. L'analisi della letteratura scientifica pertinente alla materia mostra come non sia possibile attribuire ai metodi ed ai software presenti sul mercato la valenza di raccoglitori omnicomprensivi di informazione: questo approccio olistico costituisce invece il fondamento della modellazione integrata intesa come originale processo di rappresentazione della conoscenza, ordinata secondo il paradigma delle "scatole cinesi", modello evolvente che unifica linguaggi appartenenti ai differenti attori compartecipanti nei settori impiantistici, strutturali e della visualizzazione avanzata. Evidenziando criticamente i pregi e i limiti operativi derivanti dalla modellazione integrata, la componente sperimentale della ricerca è stata articolata con l'approfondimento di esperienze condotte in contesti accademici e professionali. Il risultato conseguito ha coniugato le tecniche di rilevamento alle potenzialità di "modelli tridimensionali intelligenti", dotati cioè di criteri discriminanti per la valutazione del relazionamento topologico dei componenti con l'insieme globale.