Política de desenvolvimento rural na União Europeia: agricultura, ambiente e território

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Ordenamento do Território e Planeamento Ambiental

Os determinantes da estrutura de capital das empresas exportadoras portuguesas

Este trabalho tem como objetivo verificar os determinantes da estrutura de capital das empresas exportadoras portuguesas, comparando, sempre que possível, os resultados obtidos com outros trabalhos já desenvolvidos sobre o tema. Aplicando o Modelo dos Efeitos Fixos (MEF) a uma amostra de 7.001 empresas no período 2007-2013, concluiu-se que os determinantes com maior significância no nível de endividamento empresarial são: a rendibilidade, a dimensão, o crescimento e ainda os outros benefícos fiscais. Em relação às exportações, verificou-se através da variável dummy “exportar”, que o facto de as empresas terem exportações superiores a 10% das vendas totais, têm uma relação positiva com o endividamento de médio e longo prazo mas negativa com o endividamento de curto prazo. Perante estes resultados admitimos que as empresas exportadoras ao diversificarem (na fase inicial) o seu portfólio de clientes conseguem maiores níveis de cash-flows, o que as dispensa de algum endividamento de curto prazo, mas no médio e longo prazo as necessidades de investimento para fazer face a mercados muito competitivos está associada a um maior nível de endividamento. Relativamente à importância explicativa das variáveis “peso das vendas para o mercado comunitário” e “peso das vendas para o mercado extra comunitário”, curiosamente, apresentam resultados diferentes; o peso das vendas para o mercado extra comunitário não revela relação significativa com o endividamento mas já o peso das vendas para o mercado comunitário tem uma relação positiva com endividamento a curto prazo e negativa com o endividamento de médio e longo prazo.

Energy-aware task mapping onto heterogeneous platforms using DVFS and sleep states

Heterogeneous multicore platforms are becoming an interesting alternative for embedded computing systems with limited power supply as they can execute specific tasks in an efficient manner. Nonetheless, one of the main challenges of such platforms consists of optimising the energy consumption in the presence of temporal constraints. This paper addresses the problem of task-to-core allocation onto heterogeneous multicore platforms such that the overall energy consumption of the system is minimised. To this end, we propose a two-phase approach that considers both dynamic and leakage energy consumption: (i) the first phase allocates tasks to the cores such that the dynamic energy consumption is reduced; (ii) the second phase refines the allocation performed in the first phase in order to achieve better sleep states by trading off the dynamic energy consumption with the reduction in leakage energy consumption. This hybrid approach considers core frequency set-points, tasks energy consumption and sleep states of the cores to reduce the energy consumption of the system. Major value has been placed on a realistic power model which increases the practical relevance of the proposed approach. Finally, extensive simulations have been carried out to demonstrate the effectiveness of the proposed algorithm. In the best-case, savings up to 18% of energy are reached over the first fit algorithm, which has shown, in previous works, to perform better than other bin-packing heuristics for the target heterogeneous multicore platform.

A framework for memory contention analysis in multi-core platforms

The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often offset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work handles diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework addresses the diversity problem by applying it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.

Analysis of self-interference within DAG tasks

6th Real-Time Scheduling Open Problems Seminar (RTSOPS 2015), Lund, Sweden.

An Execution Model for Fine-Grained Parallelism in Ada

20th International Conference on Reliable Software Technologies - Ada-Europe 2015 (Ada-Europe 2015), 25 to 29, Jun, 2015. Madrid, Spain. Best Paper Award.

Real-Time Fine-Grained Parallelism in Ada

International Real-Time Ada Workshop (IRTAW 2015). 20 to 22, Apr, 2015. Pownal, U.S.A..

A Multi-DAG Model for Real-Time Parallel Applications with Conditional Execution

The 30th ACM/SIGAPP Symposium On Applied Computing (SAC 2015). 13 to 17, Apr, 2015, Embedded Systems. Salamanca, Spain.

A system model and stack for the parallelization of time-critical applications on many-core architectures

3rd Workshop on High-performance and Real-time Embedded Systems (HIRES 2015). 21, Jan, 2015. Amsterdam, Netherlands.

Semi-Partitioned Scheduling of Fork-Join Tasks using Work-Stealing

13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2015). 21 to 23, Oct, 2015, Session W1-A: Multiprocessing and Multicore Architectures. Porto, Portugal.

Real-Time Support in the Proposal for Fine-Grained Parallelism in Ada

Presented at Work in Progress Session, IEEE Real-Time Systems Symposium (RTSS 2015). 1 to 3, Dec, 2015. San Antonio, U.S.A..

Real-time Parallel Applications on Many-core Architectures

Presented at INForum - Simpósio de Informática (INFORUM 2015). 7 to 8, Sep, 2015. Portugal.

Using Quicktrace to collect runtime execution traces easily and automatically

IEEE Real-Time Systems Symposium (RTSS 2015). 1 to 4, Dec, 2015. U.S.A.

Parallel Software framework for time-critical many-core systems

The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. On one side, new kinds of HPC applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time. On the other side, EC systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures. The advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictable high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. To this end, it is of paramount importance to develop new techniques for exploiting the massively parallel computation capabilities of such platforms in a predictable way. P-SOCRATES will tackle this important challenge by merging leading research groups from the HPC and EC communities. The time-criticality and parallelisation challenges common to both areas will be addressed by proposing an integrated framework for executing workload-intensive applications with real-time requirements on top of next-generation commercial-off-the-shelf (COTS) platforms based on many-core accelerated architectures. The project will investigate new HPC techniques that fulfil real-time requirements. The main sources of indeterminism will be identified, proposing efficient mapping and scheduling algorithms, along with the associated timing and schedulability analysis, to guarantee the real-time and performance requirements of the applications.

Pesquisa de novos metabolitos secundários bioactivos em bactérias de sedimentos marinhos

Dissertação para obtenção do Grau de Mestre em Genética Molecular e Biomedicina