Mechatronic system for ABO human blood typing

In medical emergency situations, when a patient needs a blood transfusion, the universal blood type O− is administered. This procedure may lead to the depletion of stock reserves of O− blood. Nowadays, there is no commercial equipment capable of determining the patient's blood type in situ, in a fast and reliable process. Human blood typing is usually performed through the manual test, which involves a macroscopic observation and interpretation of the results by an analyst. This test, despite of having a fast response time, may lead to human errors, which sometimes can be fatal to the patient. This paper presents the development of an automatic mechatronic prototype for determining human blood typing (ABO and Rh systems) through image processing techniques. The prototype design takes into account the characteristics of reliability of analysis, portability, and response time allowing the system to be used in emergency situations. The developed prototype performs blood and reagents mixture acquires the resultant image and processes the data (based on image processing techniques) to determine the sample blood type. It was tested in a laboratory, using cataloged samples of blood types, provided by the Portuguese Institute of Blood and Transplantation. Hereafter, it is expected to test and validate the prototype in clinical environments.

Embedded platform for ECG biometric recognition

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

Automatic synthesis of VHDL Hardware Components from IOPT Petri Net models

Conferência: 39th Annual Conference of the IEEE Industrial-Electronics-Society (IECON), Vienna, Austria, Nov 10-14, 2013

Ferramenta de apoio ao projeto, configuração e gestão de instalações domóticas

Esta dissertação apresenta o trabalho realizado no âmbito da unidade curricular de Tese / Dissertação (TEDI) do Mestrado em Engenharia Eletrotécnica e de Computadores – Especialização em Automação e Sistemas em parceria com a empresa Live Simply, uma empresa de domótica que decidiu apostar na inovação e no desenvolvimento de serviços e produtos de valor acrescentado para consolidar a sua posição no mercado. Neste contexto, foram identificadas como mais-valias para a Live Simply a conceção, por um lado, de uma ferramenta de apoio técnico de integração e simplificação das fases de projeto, configuração e gestão de instalações domóticas e, por outro lado, de uma interface com a instalação para o cliente consultar e alterar, em tempo real, o estado dos atuadores. Depois de analisadas as tecnologias disponíveis, selecionaram-se as soluções a adotar (linguagens de programação, servidores de base de dados e ambientes de desenvolvimento), definiu-se a arquitetura do sistema, detalhando-se os módulos de projeto, configuração e gestão de instalações, a estrutura da base de dados assim como o hardware de controlo da instalação. De seguida, procedeu-se ao desenvolvimento dos módulos de software e à configuração e programação do módulo de hardware. Por último, procedeu-se a um conjunto exaustivo de testes aos diferentes módulos que demonstraram o correto funcionamento da ferramenta e a adequação das tecnologias empregues. A ferramenta de apoio técnico realizada integra as fases do projeto, configuração e gestão de instalações domóticas, permitindo melhorar o desempenho dos técnicos e a resposta aos clientes. A interface oferecida ao dono da instalação é uma interface Web de aspeto amigável e fácil utilização que permite consultar e modificar em tempo real o estado da instalação.

Distributed active traction control system applied to the RoboCup middle size league

This work addresses the problem of traction control in mobile wheeled robots in the particular case of the RoboCup Middle Size League (MSL). The slip control problem is formulated using simple friction models for ISePorto Team robots with a differential wheel configuration. Traction was also characterized experimentally in the MSL scenario for relevant game events. This work proposes a hierarchical traction control architecture which relies in local slip detection and control at each wheel, with relevant information being relayed to a higher level responsible for global robot motion control. A dedicated one axis control embedded hardware subsystem allowing complex local control, high frequency current sensing and odometric information procession was developed. This local axis control board is integrated in a distributed system using CAN bus communications. The slipping observer was implemented in the axis control hardware nodes integrated in the ISePorto robots and was used to control and detect loss of for traction. %and to detect the ball in the kicking device. An external vision system was used to perform a qualitative analysis of the slip detection and observer performance results are presented.

A traffic differentiation add-on to the IEEE 802.15.4 protocol: implementation and experimental validation over a real-time operating system

The IEEE 802.15.4 is the most widespread used protocol for Wireless Sensor Networks (WSNs) and it is being used as a baseline for several higher layer protocols such as ZigBee, 6LoWPAN or WirelessHART. Its MAC (Medium Access Control) supports both contention-free (CFP, based on the reservation of guaranteed time-slots GTS) and contention based (CAP, ruled by CSMA/CA) access, when operating in beacon-enabled mode. Thus, it enables the differentiation between real-time and best-effort traffic. However, some WSN applications and higher layer protocols may strongly benefit from the possibility of supporting more traffic classes. This happens, for instance, for dense WSNs used in time-sensitive industrial applications. In this context, we propose to differentiate traffic classes within the CAP, enabling lower transmission delays and higher success probability to timecritical messages, such as for event detection, GTS reservation and network management. Building upon a previously proposed methodology (TRADIF), in this paper we outline its implementation and experimental validation over a real-time operating system. Importantly, TRADIF is fully backward compatible with the IEEE 802.15.4 standard, enabling to create different traffic classes just by tuning some MAC parameters.

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores

Remote operation of embedded controllers designed using IOPT Petri-nets

This paper presents a new communication architecture to enable the remote control, monitoring and debug of embedded-system controllers designed using IOPT Petri nets. IOPT Petri nets and the related tools (http://gres.uninova.pt) have been used as a rapid prototyping and development framework, including model-checking, simulation and automatic code generation tools. The new architecture adds remote operation capabilities to the controllers produced by the automatic code generators, enabling quasi-real-time remote debugging and monitoring using the IOPT simulator tool. Furthermore, it enables the creation of graphical user interfaces for remote operation and the development of distributed systems where a Petri net model running on a central system supervises the actions of multiple remote subsystems. © 2015 IEEE.

Development of a system to monitor surfer’s balance and plantar pressure and surfboard’s movement

O uso da tecnologia tem crescido nas últimas décadas nas mais diversas áreas, seja na indústria ou no dia-a-dia, e é cada vez mais evidente os benefícios que traz. No desporto não é diferente. Cada dia surgem novos desenvolvimentos objetivando a melhoria do desempenho dos praticantes de atividades físicas, possibilitando atingir resultados nunca antes pensados. Além disto, a utilização da tecnologia no desporto permite a obtenção de dados biomecânicos que podem ser utilizados tanto no treinamento quando na melhoria da qualidade de vida dos atletas auxiliando na prevenção de lesões, por exemplo. Deste modo, o presente projeto se aplica na área do desporto, nomeadamente, na modalidade do surfe, onde a ausência de trabalhos científicos ainda é elevada, aliando a tecnologia eletrônica ao desporto para quantificar informações até então desconhecidas. Três fatores básicos de desempenho foram levantados, sendo eles: equilíbrio, posicionamento dos pés e movimentação da prancha de surfe. Estes fatores levaram ao desenvolvimento de um sistema capaz de medi-los dinamicamente através da medição das forças plantares e da rotação da prancha de surfe. Além da medição dos fatores, o sistema é capaz de armazenar os dados adquiridos localmente através de um cartão de memória, para posterior análise; e também enviá-los através de uma comunicação sem fio, permitindo a visualização do centro de pressões plantares; dos ângulos de rotação da prancha de surfe; e da ativação dos sensores; em tempo real. O dispositivo consiste em um sistema eletrônico embarcado composto por um microcontrolador ATMEGA1280; um circuito de aquisição e condicionamento de sinal analógico; uma central inercial; um módulo de comunicação sem fio RN131; e um conjunto de sensores de força Flexiforce. O firmware embarcado foi desenvolvido em linguagem C. O software Matlab foi utilizado para receção de dados e visualização em tempo real. Os testes realizados demostraram que o funcionamento do sistema atende aos requisitos propostos, fornecendo informação acerca do equilíbrio, através do centro de pressões; do posicionamento dos pés, através da distribuição das pressões plantares; e do movimento da prancha nos eixos pitch e roll, através da central inercial. O erro médio de medição de força verificado foi de -0.0012 ± 0.0064 N, enquanto a mínima distância alcançada na transmissão sem fios foi de 100 m. A potência medida do sistema foi de 330 mW.

Intra-Task Device Scheduling for Real-Time Embedded Systems

An ever increasing need for extra functionality in a single embedded system demands for extra Input/Output (I/O) devices, which are usually connected externally and are expensive in terms of energy consumption. To reduce their energy consumption, these devices are equipped with power saving mechanisms. While I/O device scheduling for real-time (RT) systems with such power saving features has been studied in the past, the use of energy resources by these scheduling algorithms may be improved. Technology enhancements in the semiconductor industry have allowed the hardware vendors to reduce the device transition and energy overheads. The decrease in overhead of sleep transitions has opened new opportunities to further reduce the device energy consumption. In this research effort, we propose an intra-task device scheduling algorithm for real-time systems that wakes up a device on demand and reduces its active time while ensuring system schedulability. This intra-task device scheduling algorithm is extended for devices with multiple sleep states to further minimise the overall device energy consumption of the system. The proposed algorithms have less complexity when compared to the conservative inter-task device scheduling algorithms. The system model used relaxes some of the assumptions commonly made in the state-of-the-art that restrict their practical relevance. Apart from the aforementioned advantages, the proposed algorithms are shown to demonstrate the substantial energy savings.

DEWI - Wirelessly into the Future

Euromicro Conference on Digital System Design (DSD2015), EPDSD - 3rd European Projects in Digital System Design, Funchal, Portugal.

Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures

As of today, AUTOSAR is the de facto standard in the automotive industry, providing a common software architec- ture and development process for automotive applications. While this standard is originally written for singlecore operated Elec- tronic Control Units (ECU), new guidelines and recommendations have been added recently to provide support for multicore archi- tectures. This update came as a response to the steady increase of the number and complexity of the software functions embedded in modern vehicles, which call for the computing power of multicore execution environments. In this paper, we enumerate and analyze the design options and the challenges of porting AUTOSAR-based automotive applications onto multicore platforms. In particular, we investigate those options when considering the emerging many- core architectures that provide a more scalable environment than the traditional multicore systems. Such platforms are suitable to enable massive parallel execution, and their design is more suitable for partitioning and isolating the software components.

Methodologies for the WCET Analysis of Parallel Applications on Many-core Architectures

Euromicro Conference on Digital System Design (DSD 2015), Funchal, Portugal.