Provably Good Task Assignment for Two-Type Heterogeneous Multiprocessors Using Cutting Planes

Consider scheduling of real-time tasks on a multiprocessor where migration is forbidden. Specifically, consider the problem of determining a task-to-processor assignment for a given collection of implicit-deadline sporadic tasks upon a multiprocessor platform in which there are two distinct types of processors. For this problem, we propose a new algorithm, LPC (task assignment based on solving a Linear Program with Cutting planes). The algorithm offers the following guarantee: for a given task set and a platform, if there exists a feasible task-to-processor assignment, then LPC succeeds in finding such a feasible task-to-processor assignment as well but on a platform in which each processor is 1.5 × faster and has three additional processors. For systems with a large number of processors, LPC has a better approximation ratio than state-of-the-art algorithms. To the best of our knowledge, this is the first work that develops a provably good real-time task assignment algorithm using cutting planes.

Efficient schedulability tests for real-time embedded systems with urgent routines

Task scheduling is one of the key mechanisms to ensure timeliness in embedded real-time systems. Such systems have often the need to execute not only application tasks but also some urgent routines (e.g. error-detection actions, consistency checkers, interrupt handlers) with minimum latency. Although fixed-priority schedulers such as Rate-Monotonic (RM) are in line with this need, they usually make a low processor utilization available to the system. Moreover, this availability usually decreases with the number of considered tasks. If dynamic-priority schedulers such as Earliest Deadline First (EDF) are applied instead, high system utilization can be guaranteed but the minimum latency for executing urgent routines may not be ensured. In this paper we describe a scheduling model according to which urgent routines are executed at the highest priority level and all other system tasks are scheduled by EDF. We show that the guaranteed processor utilization for the assumed scheduling model is at least as high as the one provided by RM for two tasks, namely 2(2√−1). Seven polynomial time tests for checking the system timeliness are derived and proved correct. The proposed tests are compared against each other and to an exact but exponential running time test.

Remote operation of embedded controllers designed using IOPT Petri-nets

This paper presents a new communication architecture to enable the remote control, monitoring and debug of embedded-system controllers designed using IOPT Petri nets. IOPT Petri nets and the related tools (http://gres.uninova.pt) have been used as a rapid prototyping and development framework, including model-checking, simulation and automatic code generation tools. The new architecture adds remote operation capabilities to the controllers produced by the automatic code generators, enabling quasi-real-time remote debugging and monitoring using the IOPT simulator tool. Furthermore, it enables the creation of graphical user interfaces for remote operation and the development of distributed systems where a Petri net model running on a central system supervises the actions of multiple remote subsystems. © 2015 IEEE.

High-level Petri nets modules for embedded controllers design

Modular design is crucial to manage large-scale systems and to support the divide-and-conquer development approach. It allows hierarchical representations and, therefore, one can have a system overview, as well as observe component details. Petri nets are suitable to model concurrent systems, but lack on structuring mechanisms to support abstractions and the composition of sub-models, in particular when considering applications to embedded controllers design. In this paper we present a module construct, and an underlying high-level Petri net type, to model embedded controllers. Multiple interfaces can be declared in a module, thus, different instances of the same module can be used in different situations. The interface is a subset of the module nodes, through which the communication with the environment is made. Module places can be annotated with a generic type, overridden with a concrete type at instance level, and constants declared in a module may have a new value in each instance.

Strap repairs using embedded patches: numerical analysis and experimental results

Adhesively bonded repairs offer an attractive option for repair of aluminium structures, compared to more traditional methods such as fastening or welding. The single-strap (SS) and double-strap (DS) repairs are very straightforward to execute but stresses in the adhesive layer peak at the overlap ends. The DS repair requires both sides of the damaged structures to be reachable for repair, which is often not possible. In strap repairs, with the patches bonded at the outer surfaces, some limitations emerge such as the weight, aerodynamics and aesthetics. To minimize these effects, SS and DS repairs with embedded patches were evaluated in this work, such that the patches are flush with the adherends. For this purpose, in this work standard SS and DS repairs, and also with the patches embedded in the adherends, were tested under tension to allow the optimization of some repair variables such as the overlap length (LO) and type of adhesive, thus allowing the maximization of the repair strength. The effect of embedding the patch/patches on the fracture modes and failure loads was compared with finite elements (FE) analysis. The FE analysis was performed in ABAQUS® and cohesive zone modelling was used for the simulation of damage onset and growth in the adhesive layer. The comparison with the test data revealed an accurate prediction for all kinds of joints and provided some principles regarding this technique.

A fractional perspective to financial indices

The application of mathematical methods and computer algorithms in the analysis of economic and financial data series aims to give empirical descriptions of the hidden relations between many complex or unknown variables and systems. This strategy overcomes the requirement for building models based on a set of ‘fundamental laws’, which is the paradigm for studying phenomena usual in physics and engineering. In spite of this shortcut, the fact is that financial series demonstrate to be hard to tackle, involving complex memory effects and a apparently chaotic behaviour. Several measures for describing these objects were adopted by market agents, but, due to their simplicity, they are not capable to cope with the diversity and complexity embedded in the data. Therefore, it is important to propose new measures that, on one hand, are highly interpretable by standard personal but, on the other hand, are capable of capturing a significant part of the dynamical effects.

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.

Visible range plasmonic effect produced by aluminium nanoparticles embedded in amorphous silicon

We present results, obtained by means of an analytic study and a numerical simulation, about the resonant condition necessary to produce a Localized Surface Plasmonic Resonance (LSPR) effect at the surface of metal nanospheres embedded in an amorphous silicon matrix. The study is based on a Lorentz dispersive model for a-Si:H permittivity and a Drude model for the metals. Considering the absorption spectra of a-Si:H, the best choice for the metal nanoparticles appears to be aluminium, indium or magnesium. No difference has been observed when considering a-SiC:H. Finite-difference time-domain (FDTD) simulation of an Al nanosphere embedded into an amorphous silicon matrix shows an increased scattering radius and the presence of LSPR induced by the metal/semiconductor interaction under green light (560 nm) illumination. Further results include the effect of the nanoparticles shape (nano-ellipsoids) in controlling the wavelength suitable to produce LSPR. It has been shown that is possible to produce LSPR in the red part of the visible spectrum (the most critical for a-Si:H solar cells applications in terms of light absorption enhancement) with aluminium nano-ellipsoids. As an additional results we may conclude that the double Lorentz-Lorenz model for the optical functions of a-Si:H is numerically stable in 3D simulations and can be used safely in the FDTD algorithm. A further simulation study is directed to determine an optimal spatial distribution of Al nanoparticles, with variable shapes, capable to enhance light absorption in the red part of the visible spectrum, exploiting light trapping and plasmonic effects. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Energy evaporation: the new concept of indoor systems for WPT and EH embedded into the floor

This work introduces a novel idea for wireless energy transfer, proposing for the first time the unit-cell of an indoor localization and RF harvesting system embedded into the floor. The unit-cell is composed by a 5.8 GHz patch antenna surrounded by a 13.56 MHz coil. The coil locates a device and activate the patch which, connected to a power grid, radiates to wirelessly charge the localized device. The HF and RF circuits co-existence and functionality are demonstrated in this paper, the novelty of which is also in the adoption of low cost and most of all ecofriendly materials, such as wood and cork, as substrates for electronics.

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering

Embedded system for individual recognition based on ECG biometrics

Biometric recognition is emerging has an alternative solution for applications where the privacy of the information is crucial. This paper presents an embedded biometric recognition system based on the Electrocardiographic signals (ECG) for individual identification and authentication. The proposed system implements a real-time state-of-the-art recognition algorithm, which extracts information from the frequency domain. The system is based on a ARM Cortex 4. Preliminary results show that embedded platforms are a promising path for the implementation of ECG-based applications in real-world scenario.

Projecto e implementação de osciloscópio digital baseado na norma IEEE1451.0

Os osciloscópios digitais são utilizados em diversas áreas do conhecimento, assumindo-se no âmbito da engenharia electrónica, como instrumentos indispensáveis. Graças ao advento das Field Programmable Gate Arrays (FPGAs), os instrumentos de medição reconfiguráveis, dadas as suas vantagens, i.e., altos desempenhos, baixos custos e elevada flexibilidade, são cada vez mais uma alternativa aos instrumentos tradicionalmente usados nos laboratórios. Tendo como objectivo a normalização no acesso e no controlo deste tipo de instrumentos, esta tese descreve o projecto e implementação de um osciloscópio digital reconfigurável baseado na norma IEEE 1451.0. Definido de acordo com uma arquitectura baseada nesta norma, as características do osciloscópio são descritas numa estrutura de dados denominada Transducer Electronic Data Sheet (TEDS), e o seu controlo é efectuado utilizando um conjunto de comandos normalizados. O osciloscópio implementa um conjunto de características e funcionalidades básicas, todas verificadas experimentalmente. Destas, destaca-se uma largura de banda de 575kHz, um intervalo de medição de 0.4V a 2.9V, a possibilidade de se definir um conjunto de escalas horizontais, o nível e declive de sincronismo e o modo de acoplamento com o circuito sob análise. Arquitecturalmente, o osciloscópio é constituído por um módulo especificado com a linguagem de descrição de hardware (HDL, Hardware Description Language) Verilog e por uma interface desenvolvida na linguagem de programação Java®. O módulo é embutido numa FPGA, definindo todo o processamento do osciloscópio. A interface permite o seu controlo e a representação do sinal medido. Durante o projecto foi utilizado um conversor Analógico/Digital (A/D) com uma frequência máxima de amostragem de 1.5MHz e 14 bits de resolução que, devido às suas limitações, obrigaram à implementação de um sistema de interpolação multi-estágio com filtros digitais.

Electron driven reactions in complexes embedded in superfluid helium droplets

A thesis submitted to the University of Innsbruck for the doctor degree in Natural Sciences, Physics and New University of Lisbon for the doctor degree in Physics, Atomic and Molecular Physics

An integer programming framework for sequencing cutting patterns based on interval graph completion

We derived a framework in integer programming, based on the properties of a linear ordering of the vertices in interval graphs, that acts as an edge completion model for obtaining interval graphs. This model can be applied to problems of sequencing cutting patterns, namely the minimization of open stacks problem (MOSP). By making small modifications in the objective function and using only some of the inequalities, the MOSP model is applied to another pattern sequencing problem that aims to minimize, not only the number of stacks, but also the order spread (the minimization of the stack occupation problem), and the model is tested.

An integer programming model for the minimum interval graph completion problem

The minimum interval graph completion problem consists of, given a graph G = ( V, E ), finding a supergraph H = ( V, E ∪ F ) that is an interval graph, while adding the least number of edges |F| . We present an integer programming formulation for solving the minimum interval graph completion problem recurring to a characteri- zation of interval graphs that produces a linear ordering of the maximal cliques of the solution graph.