A system verification strategy based on the BST infrastructure

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia

New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise

IEEE International Symposium on Circuits and Systems, pp. 232 – 235, Seattle, EUA

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA

A CMOS variable width short-pulse generator circuit for UWB RADAR applications

IEEE International Symposium on Circuits and Systems, pp. 2713 – 2716, Seattle, EUA

Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm

IEEE International Symposium on Circuits and Systems, pp. 724 – 727, Seattle, EUA

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, Malta

Multi-bit sigma-delta modulators with enhanced dynamic-range using non-linear DAC for hearing aids

15th IEEE International Conference on Electronics, Circuits and Systems, Malta

A new blind equalization algorithm based on convex combination

The convex combination is a mathematic approach to keep the advantages of its component algorithms for better performance. In this paper, we employ convex combination in the blind equalization to achieve better blind equalization. By combining the blind constant modulus algorithm (CMA) and decision directed algorithm, the combinative blind equalization (CBE) algorithm can retain the advantages from both. Furthermore, the convergence speed of the CBE algorithm is faster than both of its component equalizers. Simulation results are also given to verify the proposed algorithm.

A novel blind channel estimation method for MIMO system

Channel estimation method is a key issue in MIMO system. In recent years, a lot of papers on subspace(SS)-based blind channel estimation have been published, and in this paper, combining SS method with a space-time coding scheme, we proposed a novel blind channel estimation method in MIMO system. Simulation result demonstrates the effectiveness of this method.

A semi-blind reception scheme based on ICA for multiuser MIMO-STBC system

When the orthogonal space-time block code (STBC), or the Alamouti code, is applied on a multiple-input multiple-output (MIMO) communications system, the optimum reception can be achieved by a simple signal decoupling at the receiver. The performance, however, deteriorates significantly in presence of co-channel interference (CCI) from other users. In this paper, such CCI problem is overcome by applying the independent component analysis (ICA), a blind source separation algorithm. This is based on the fact that, if the transmission data from every transmit antenna are mutually independent, they can be effectively separated at the receiver with the principle of the blind source separation. Then equivalently, the CCI is suppressed. Although they are not required by the ICA algorithm itself, a small number of training data are necessary to eliminate the phase and order ambiguities at the ICA outputs, leading to a semi-blind approach. Numerical simulation is also shown to verify the proposed ICA approach in the multiuser MIMO system.

Suppression of directional interference for STBC MIMO system based on beam-forming

In civil applications, many researches on MIMO technique have achieved great progress. However, we consider military applications here. Differing from civil applications, military MIMO system may face many kinds of interferences, and the interference source may even not be equipped with multiple antennas. So the military MIMO system may receive some kind of strong interference coming from certain direction. Therefore, the military MIMO system must have capability to suppress directional interference. This paper presents a scheme to suppress directional interference for STBC MIMO system based on beam-forming. Simulation result shows that the scheme is valid to suppress directional strong interference for STBC MIMO system although with some performance loss compared with the ideal case of non-interference.

Parallel Architectures for High Speed Multipliers

The authors compare various array multiplier architectures based on (p,q) counter circuits. The tradeoff in multiplier design is always between adding complexity and increasing speed. It is shown that by using a (2,2,3) counter cell it is possible to gain a significant increase in speed over a conventional full-adder, carry-save array based approach. The increase in complexity should be easily accommodated using modern emitter-coupled-logic processes.