858 resultados para Output-voltage ranges
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Nowadays, there is a boom in the use of electrification. Electric vehicles are gaining interest worldwide due to various factors, including climate and environmental awareness. In this thesis, a step-down isolated power supply for electric tractors is investigated, specifically the phase-shifted full-bridge (PSFB) DC-DC with synchronous rectification and zero-voltage switching (ZVS). This converter was selected for its high-power capacity with high efficiency. A 3500 W PSFB converter with peak current control (PCCM) is designed and modeled in MATLAB. The input voltage range is from 550 V to 820 V and the output voltage range is limited to 9 V to 16 V with a maximum output current of 250 A. All components were commercially designed and selected, including magnetics for the high-frequency transformer and inductors, taking into account loss calculations. Zero voltage switching for the lagging leg is achieved at 13% to 100% load. The proven efficiency of the converter is around 90
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Recent technological developments have created new devices that could improve and simplify the construction of stimulus isolators. HEXFET transistors can switch large currents and hundreds of volts in nanoseconds. The newer opto-isolators can give a pulse rise time of a few nanoseconds, with output compatible with MOSFET devices, in which delays are reduced to nanoseconds. Integrated DC/DC converters are now available. Using these new resources we developed a new electrical stimulus isolator circuit with selectable constant-current and constant-voltage modes, which are precise and easy to construct. The circuit works like a regulated power supply in both modes with output switched to zero or to free mode through an opto-isolator device. The isolator analyses showed good practical performance. The output to ground resistance was 1011 ohms and capacitance 35 picofarads. The rise time and fall time were identical (5 µs) and constant. The selectable voltage or current output mode made it very convenient to use. The current mode, with higher output resistance values in low current ranges, permits intracellular stimulation even with tip resistances close to 100 megaohms. The high compliance of 200 V guarantees the value of the current stimulus. The very low output resistance in the voltage mode made the device highly suitable for extracellular stimulation with low impedance electrodes. Most importantly, these characteristics were achieved with a circuit that was easy to build and modify and assembled with components available in Brazil.
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A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.
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Since the first experimental evidences of active conductances in dendrites, most neurons have been shown to exhibit dendritic excitability through the expression of a variety of voltage-gated ion channels. However, despite experimental and theoretical efforts undertaken in the past decades, the role of this excitability for some kind of dendritic computation has remained elusive. Here we show that, owing to very general properties of excitable media, the average output of a model of an active dendritic tree is a highly non-linear function of its afferent rate, attaining extremely large dynamic ranges (above 50 dB). Moreover, the model yields double-sigmoid response functions as experimentally observed in retinal ganglion cells. We claim that enhancement of dynamic range is the primary functional role of active dendritic conductances. We predict that neurons with larger dendritic trees should have larger dynamic range and that blocking of active conductances should lead to a decrease in dynamic range.
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Transmission and switching in digital telecommunication networks require distribution of precise time signals among the nodes. Commercial systems usually adopt a master-slave (MS) clock distribution strategy building slave nodes with phase-locked loop (PLL) circuits. PLLs are responsible for synchronizing their local oscillations with signals from master nodes, providing reliable clocks in all nodes. The dynamics of a PLL is described by an ordinary nonlinear differential equation, with order one plus the order of its internal linear low-pass filter. Second-order loops are commonly used because their synchronous state is asymptotically stable and the lock-in range and design parameters are expressed by a linear equivalent system [Gardner FM. Phaselock techniques. New York: John Wiley & Sons: 1979]. In spite of being simple and robust, second-order PLLs frequently present double-frequency terms in PD output and it is very difficult to adapt a first-order filter in order to cut off these components [Piqueira JRC, Monteiro LHA. Considering second-harmonic terms in the operation of the phase detector for second order phase-locked loop. IEEE Trans Circuits Syst [2003;50(6):805-9; Piqueira JRC, Monteiro LHA. All-pole phase-locked loops: calculating lock-in range by using Evan`s root-locus. Int J Control 2006;79(7):822-9]. Consequently, higher-order filters are used, resulting in nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on parameters combinations, can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing synchronization ranges. In this work, we consider a second-order Sallen-Key loop filter [van Valkenburg ME. Analog filter design. New York: Holt, Rinehart & Winston; 1982] implying a third order PLL The resulting lock-in range of the third-order PLL is determined by two bifurcation conditions: a saddle-node and a Hopf. (C) 2008 Elsevier B.V. All rights reserved.
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This paper presents a predictive optimal matrix converter controller for a flywheel energy storage system used as Dynamic Voltage Restorer (DVR). The flywheel energy storage device is based on a steel seamless tube mounted as a vertical axis flywheel to store kinetic energy. The motor/generator is a Permanent Magnet Synchronous Machine driven by the AC-AC Matrix Converter. The matrix control method uses a discrete-time model of the converter system to predict the expected values of the input and output currents for all the 27 possible vectors generated by the matrix converter. An optimal controller minimizes control errors using a weighted cost functional. The flywheel and control process was tested as a DVR to mitigate voltage sags and swells. Simulation results show that the DVR is able to compensate the critical load voltage without delays, voltage undershoots or overshoots, overcoming the input/output coupling of matrix converters.
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Visible range to telecom band spectral translation is accomplished using an amorphous SiC pi'n/pin wavelength selector under appropriate front and back optical light bias. Results show that background intensity works as selectors in the infrared region, shifting the sensor sensitivity. Low intensities select the near-infrared range while high intensities select the visible part according to its wavelength. Here, the optical gain is very high in the infrared/red range, decreases in the green range, stays close to one in the blue region and strongly decreases in the near-UV range. The transfer characteristics effects due to changes in steady state light intensity and wavelength backgrounds are presented. The relationship between the optical inputs and the output signal is established. A capacitive optoelectronic model is presented and tested using the experimental results. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
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Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e Computadores
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Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores
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The aim of this thesis is to investigate the thermal loading of medium voltage three-level NPC inverter’s semiconductor IGCT switches in different operation points. The objective is to reach both a fairly accurate off-line simulation program and also so simple a simulation model that its implementation into an embedded system could be reasonable in practice and a real time use should become feasible. Active loading limitation of the inverter can be realized with a thermal model which is practical in a real time use. Determining of the component heating has been divided into two parts; defining of component losses and establishing the structure of a thermal network. Basics of both parts are clarified. The simulation environment is Matlab-Simulink. Two different models are constructed – a more accurate one and a simplified one. Potential simplifications are clarified with the help of the first one. Simplifications are included in the latter model and the functionalities of both models are compared. When increasing the calculation time step a decreased number of considered components and time constants of the thermal network can be used in the simplified model. Heating of a switching component is dependent on its topological position and inverter’s operation point. The output frequency of the converter defines mainly which one of the switching components is – because of its losses and heating – the performance limiting component of the converter. Comparison of results given by different thermal models demonstrates that with larger time steps, describing of fast occurring switching losses becomes difficult. Generally articles and papers dealing with this subject are written for two-level inverters. Also inverters which apply direct torque control (DTC) are investigated rarely from the heating point of view. Hence, this thesis completes the former material.
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In recent years, the network vulnerability to natural hazards has been noticed. Moreover, operating on the limits of the network transmission capabilities have resulted in major outages during the past decade. One of the reasons for operating on these limits is that the network has become outdated. Therefore, new technical solutions are studied that could provide more reliable and more energy efficient power distributionand also a better profitability for the network owner. It is the development and price of power electronics that have made the DC distribution an attractive alternative again. In this doctoral thesis, one type of a low-voltage DC distribution system is investigated. Morespecifically, it is studied which current technological solutions, used at the customer-end, could provide better power quality for the customer when compared with the current system. To study the effect of a DC network on the customer-end power quality, a bipolar DC network model is derived. The model can also be used to identify the supply parameters when the V/kW ratio is approximately known. Although the model provides knowledge of the average behavior, it is shown that the instantaneous DC voltage ripple should be limited. The guidelines to choose an appropriate capacitance value for the capacitor located at the input DC terminals of the customer-end are given. Also the structure of the customer-end is considered. A comparison between the most common solutions is made based on their cost, energy efficiency, and reliability. In the comparison, special attention is paid to the passive filtering solutions since the filter is considered a crucial element when the lifetime expenses are determined. It is found out that the filter topology most commonly used today, namely the LC filter, does not provide economical advantage over the hybrid filter structure. Finally, some of the typical control system solutions are introduced and their shortcomings are presented. As a solution to the customer-end voltage regulation problem, an observer-based control scheme is proposed. It is shown how different control system structures affect the performance. The performance meeting the requirements is achieved by using only one output measurement, when operating in a rigid network. Similar performance can be achieved in a weak grid by DC voltage measurement. An additional improvement can be achieved when an adaptive gain scheduling-based control is introduced. As a conclusion, the final power quality is determined by a sum of various factors, and the thesis provides the guidelines for designing the system that improves the power quality experienced by the customer.
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Motivation: There is a frequent need to apply a large range of local or remote prediction and annotation tools to one or more sequences. We have created a tool able to dispatch one or more sequences to assorted services by defining a consistent XML format for data and annotations. Results: By analyzing annotation tools, we have determined that annotations can be described using one or more of the six forms of data: numeric or textual annotation of residues, domains (residue ranges) or whole sequences. With this in mind, XML DTDs have been designed to store the input and output of any server. Plug-in wrappers to a number of services have been written which are called from a master script. The resulting APATML is then formatted for display in HTML. Alternatively further tools may be written to perform post-analysis.
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An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.
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A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.
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A robust 12 kW rectifier with low THD in the line currents, based on an 18-pulse transformer arrangement with reduced kVA capacities followed by a high-frequency isolation stage is presented in this work. Three full-bridge (buck-based) converters are used to allow galvanic isolation and to balance the dc-link currents, without current sensing or current controller. The topology provides a regulated dc output with a very simple and well-known control strategy and natural three-phase power factor correction. The phase-shift PWM technique, with zero-voltage switching is used for the high-frequency dc-dc stage. Analytical results from Fourier analysis of winding currents and the vector diagram of winding voltages are presented. Experimental results from a 12 kW prototype are shown in the paper to verify the efficiency, robustness and simplicity of the command circuitry to the proposed concept.