Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

BRST invariant theory of a generalized 1+1 Dimensional nonlinear sigma model with topological term

We give a generalized Lagrangian density of 1 + 1 Dimensional O( 3) nonlinear sigma model with subsidiary constraints, different Lagrange multiplier fields and topological term, find a lost intrinsic constraint condition, convert the subsidiary constraints into inner constraints in the nonlinear sigma model, give the example of not introducing the lost constraint. N = 0, by comparing the example with the case of introducing the lost constraint, we obtain that when not introducing the lost constraint, one has to obtain a lot of various non-intrinsic constraints. We further deduce the gauge generator, give general BRST transformation of the model under the general conditions. It is discovered that there exists a gauge parameter beta originating from the freedom degree of BRST transformation in a general O( 3) nonlinear sigma model, and we gain the general commutation relations of ghost field.

伴随法在潮汐和海温数值计算中的应用研究

变分数据同化中的伴随法可实现数值模型与观测数据的拟合。随着物理海洋数值计算和数值预报业务的不断发展，其具有广阔的应用前景。本文主要研究关于伴随数据同化的有关理论及其在物理海洋数值模型中的应用。本文介绍了变分伴随数据同化的基本原理，从模型方程的连续和离散形式出发讨论采用两种不同的方法推导伴随方程，一是拉格朗日乘子（Lagrange multiplier）法；二是基于泛函的Gateaux微分概念的方法，这里简称Gateaux微分法。文中讨论了导出离散伴随模型方程和目标函数梯度的两种不同途径，其中一种途径是由连续的正模型得到连续的伴随模型及连续的目标函数梯度表达式，然后再对伴随模型和目标函数梯度进行差分离散（简称“伴随的差分”）；另外一种途径是由离散的正模型直接导出离散的伴随模型及梯度表达式（简称“差分的伴随”）。目前尽管人们比较一致的看法是应该采用后一种途径，即建立伴随模型系统应该采用“差分的伴随”，但对由这两种途径建立的伴随系统的相互关系，人们探讨的并不多。本文利用了简单的模型对该问题进行了研究。另外，对有关初始猜测和伴随优化系统的多解性问题进行了探讨。本文着重研究并实现了利用伴随法优化非线性潮汐模型的开边界条件。其中采用的二维非线性浅水模型既考虑非线性底磨擦和侧向粘性涡动混合，又包括非线性平流项；离散伴随模型的建立是基于ADI格式（不受CFL条件限制），改善了变分伴随数据同化过程中计算量和计算存储问题，使之减小若干倍（约5～7倍），从而使得模式适于业务化的需求，具有实用价值；同化过程中使用的观测数据既包括常规验潮站水位观测资料，又包括TOPEX/POSEIDON卫星测高数据。实测数据同化数值试验表明，开边界条件的最优控制对数值计算结果有一定程度的改进。本文还探讨了将伴随法应用于海表面温度（SST）的数值预报中。其中采用的SST数值预报模型是基于国家“七五”期间科技攻关项目《中国近海海表面温度短期数值预报模式》。文中利用船舶报SST观测数据进行伴随数据同化试验，以优化初始场，其结果是比较满意的，表明变分数据同化对改进SST数值预报的效果是比较明显的，将伴随法引入中国海域SST数值预报业务化中是可行的。本文最后讨论了伴随数据同化中尚待深入研究的问题，着重指出了在物理海洋学领域开展二阶伴随模式应用研究的内容和必要性。

Winkler springs (p-y curves) for liquefied soil from element tests.

In practice, piles are most often modelled as "Beams on Non-Linear Winkler Foundation" (also known as “p-y spring” approach) where the soil is idealised as p-y springs. These p-y springs are obtained through semi-empirical approach using element test results of the soil. For liquefied soil, a reduction factor (often termed as p-multiplier approach) is applied on a standard p-y curve for the non-liquefied condition to obtain the p-y curve liquefied soil condition. This paper presents a methodology to obtain p-y curves for liquefied soil based on element testing of liquefied soil considering physically plausible mechanisms. Validation of the proposed p-y curves is carried out through the back analysis of physical model tests.

Trade credit linkages along the supply chain: evidence for the Italian textile sector

We examine the trade credit linkages among firms within a supply chain to reckon the effect of such linkages on the propagation of liquidity shocks from downstream to upstream firms. We choose a sample appropriate for this task, consisting of a large data set of Italian firms from the textile industry, a well known example of a comprehensive manufacturing cluster featuring a large number of small and specialized firms at each level of the supply chain. The results of the analysis indicate that the level of trade credit that firms provide to their suppliers is positively related to the level of trade credit granted to their clients: when the level of trade credit granted to clients divided by sales goes up by 1, the level of trade credit provided to suppliers divided by cost-of goods-sold goes up by an amount that varies between 0,22 and 0,52. Since all firms along the chain are linked by trade credit relationships, an increase in the level of trade credit granted by wholesalers generates a liquidity cascade throughout the chain. We designate the overall increase in the level of trade credit among all firms in the chain as a result of a unitary impulse in the level of trade credit granted by wholesalers as the multiplier effect of trade credit for the industry chain. We estimate such multiplier to vary between 1.28 and 2.04. We also investigate the effect of final demand on the level of trade credit sourced by firms at various levels of the chain and, in particular, whether such effect is amplified for firms further up in the chain as a result of liquidity propagation via trade credit linkages. We uncover evidence of such amplification when the links of liquidity transmission along the chain are individually modeled and estimated. An unitary increase in wholesalers’ sales is found to produce an effect on trade payables among firms at the top of the chain (i.e., Preparers and Spinners) that is more than twice as big as the corresponding effect among firms at the bottom of the chain (i.e., Wholesalers).

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Maximal C*-algebras of quotients and injective envelopes of C*-algebras

A new C*-enlargement of a C*-algebra A nested between the local multiplier algebra of A and its injective envelope is introduced. Various aspects of this maximal C*-algebra of quotients are studied, notably in the setting of AW*-algebras. As a by-product we obtain a new example of a type I C*-algebra such that its second iterated local multiplier algebra is strictly larger than its local multiplier algebra.

Sheaves of C*-algebras

We develop the basics of a theory of sheaves of C*-algebras and, in particular, compare it to the existing theory of C*-bundles. The details of two fundamental examples, the local multiplier sheaf and the injective envelope sheaf, are discussed.

Compactness properties of operator multipliers

We continue the study of multidimensional operator multipliers initiated in~cite{jtt}. We introduce the notion of the symbol of an operator multiplier. We characterise completely compact operator multipliers in terms of their symbol as well as in terms of approximation by finite rank multipliers. We give sufficient conditions for the sets of compact and completely compact multipliers to coincide and characterise the cases where an operator multiplier in the minimal tensor product of two C*-algebras is automatically compact. We give a description of multilinear modular completely compact completely bounded maps defined on the direct product of finitely many copies of the C*-algebra of compact operators in terms of tensor products, generalising results of Saar

Closable multipliers

Let $(X,\mu)$ and $(Y,\nu)$ be standard measure spaces. A function $\nph\in L^\infty(X\times Y,\mu\times\nu)$ is called a (measurable) Schur multiplier if the map $S_\nph$, defined on the space of Hilbert-Schmidt operators from $L_2(X,\mu)$ to $L_2(Y,\nu)$ by multiplying their integral kernels by $\nph$, is bound-ed in the operator norm. The paper studies measurable functions $\nph$ for which $S_\nph$ is closable in the norm topology or in the weak* topology. We obtain a characterisation of w*-closable multipliers and relate the question about norm closability to the theory of operator synthesis. We also study multipliers of two special types: if $\nph$ is of Toeplitz type, that is, if $\nph(x,y)=f(x-y)$, $x,y\in G$, where $G$ is a locally compact abelian group, then the closability of $\nph$ is related to the local inclusion of $f$ in the Fourier algebra $A(G)$ of $G$. If $\nph$ is a divided difference, that is, a function of the form $(f(x)-f(y))/(x-y)$, then its closability is related to the ``operator smoothness'' of the function $f$. A number of examples of non closable, norm closable and w*-closable multipliers are presented.

FPGA montgomery modular multiplication architectures suitable for ECCs over GF(p)

New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18×18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in Elliptic Curve Cryptosystems over GF(p), which require modular field multiplication to perform elliptic curve point addition and doubling. Field sizes of 128-bits and 256-bits are chosen but other field sizes can easily be accommodated, by rapidly reprogramming the FPGA. Overall, the larger the word size of the multiplier, the more efficiently it performs in terms of area/time product. Also, the FIOS algorithm is flexible in that one can tailor the multiplier architecture is to be area efficient, time efficient or a mixture of both by choosing a particular word size. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 4.8 ms.

Design of quantum-dot cellular automata circuits using cut-set retiming

As a potential alternative to CMOS technology, QCA provides an interesting paradigm in both communication and computation. However, QCAs unique four-phase clocking scheme and timing constraints present serious timing issues for interconnection and feedback. In this work, a cut-set retiming design procedure is proposed to resolve these QCA timing issues. The proposed design procedure can accommodate QCAs unique characteristics by performing delay-transfer and time-scaling to reallocate the existing delays so as to achieve efficient clocking zone assignment. Cut-set retiming makes it possible to effectively design relatively complex QCA circuits that include feedback. It utilizes the similar characteristics of synchronization, deep pipelines and local interconnections common to both QCA and systolic architectures. As a case study, a systolic Montgomery modular multiplier is designed to illustrate the procedure. Furthermore, a nonsystolic architecture, an S27 benchmark circuit, is designed and compared with previous designs. The comparison shows that the cut-set retiming method achieves a more efficient design, with a reduction of 22%, 44%, and 46% in terms of cell count, area, and latency, respectively.

QCA Systolic array design

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology.

C∗-Segal algebras with order unit

We introduce the notion of a (noncommutative) C *-Segal algebra as a Banach algebra (A, {norm of matrix}{dot operator}{norm of matrix} A) which is a dense ideal in a C *-algebra (C, {norm of matrix}{dot operator}{norm of matrix} C), where {norm of matrix}{dot operator}{norm of matrix} A is strictly stronger than {norm of matrix}{dot operator}{norm of matrix} C onA. Several basic properties are investigated and, with the aid of the theory of multiplier modules, the structure of C *-Segal algebras with order unit is determined.