Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

One-transistor floating-body random access memory retention time distribution is investigated on silicon-on-insulator UTBOX devices. It is shown that the average retention time can be improved by two to three orders of magnitude by reducing the body-junction electric field. However, the retention time distribution, which is mainly caused by the generation-recombination center density variation, remains similar.

Estudio de utilización efectiva de procesadores vectoriales

[ES] La vectorización es un proceso de explotación de paralelismo de datos muy potente que, bien usado permite obtener un mejor rendimiento de la ejecución de las aplicaciones. Debido a ello, hoy en día muchos procesadores incluyen extensiones vectoriales en su repositorio de instrucciones. Para las máquinas basadas en estos procesadores, existen multitud de compiladores que permiten explotar la vectorización. Sin embargo, no todas las aplicaciones experimentan una mejora en el rendimiento cuando son vectorizadas, y no todos los compiladores son capaces de extraer el mismo rendimiento vectorial de las aplicaciones. Este trabajo presenta un estudio exhaustivo del rendimiento de diversas aplicaciones numéricas, con el objetivo de determinar el grado de utilización efectiva de la unidad vectorial. Tras seleccionar los benchmarks Polyhedron, Mantevo, Sequoia, SPECfp y NPB, se compilaron activando la vectorización y se simularon en una versión modificada del simulador de cache CMPSim, enriquecida con un núcleo basado en el coprocesador Intel Xeon Phitm. En aquellos casos en que la utilización era baja, se realizó un diagnóstico a nivel de software de la fuente del problema y se propusieron mejoras que podrían aumentar el uso efectivo de la unidad vectorial. Para aquellas aplicaciones limitadas por memoria, se realizó un diagnóstico a nivel de hardware con el fin de determinar hasta que punto el diseño de la máquina repercute en el rendimiento de la aplicación en casos de buen uso de la unidad vectorial.

Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures

The scale down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as they struggle to sustain the increasing tight bandwidth and latency constraints that these systems demand. The most promising solution for the future chip interconnects are the Networks on Chip (NoC). NoCs are network composed by routers and channels used to inter- connect the different components installed on the single microchip. Examples of advanced processors based on NoC interconnects are the IBM Cell processor, composed by eight CPUs that is installed on the Sony Playstation III and the Intel Teraflops pro ject composed by 80 independent (simple) microprocessors. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider and more heterogeneous world of Systems on Chip (SoC). SoC comprehend all the electronic devices that surround us such as cell-phones, smart-phones, house embedded systems, automotive systems, set-top boxes etc... SoC manufacturers such as ST Microelectronics , Samsung, Philips and also Universities such as Bologna University, M.I.T., Berkeley and more are all proposing proprietary frameworks based on NoC interconnects. These frameworks help engineers in the switch of design methodology and speed up the development of new NoC-based systems on chip. In this Thesis we propose an introduction of CMP and SoC interconnection networks. Then focusing on SoC systems we propose: • a detailed analysis based on simulation of the Spidergon NoC, a ST Microelectronics solution for SoC interconnects. The Spidergon NoC differs from many classical solutions inherited from the parallel computing world. Here we propose a detailed analysis of this NoC topology and routing algorithms. Furthermore we propose aEqualized a new routing algorithm designed to optimize the use of the resources of the network while also increasing its performance; • a methodology flow based on modified publicly available tools that combined can be used to design, model and analyze any kind of System on Chip; • a detailed analysis of a ST Microelectronics-proprietary transport-level protocol that the author of this Thesis helped developing; • a simulation-based comprehensive comparison of different network interface designs proposed by the author and the researchers at AST lab, in order to integrate shared-memory and message-passing based components on a single System on Chip; • a powerful and flexible solution to address the time closure exception issue in the design of synchronous Networks on Chip. Our solution is based on relay stations repeaters and allows to reduce the power and area demands of NoC interconnects while also reducing its buffer needs; • a solution to simplify the design of the NoC by also increasing their performance and reducing their power and area consumption. We propose to replace complex and slow virtual channel-based routers with multiple and flexible small Multi Plane ones. This solution allows us to reduce the area and power dissipation of any NoC while also increasing its performance especially when the resources are reduced. This Thesis has been written in collaboration with the Advanced System Technology laboratory in Grenoble France, and the Computer Science Department at Columbia University in the city of New York.

Temperature Variation Aware Energy Optimization in Heterogeneous MPSoCs

Thermal effects are rapidly gaining importance in nanometer heterogeneous integrated systems. Increased power density, coupled with spatio-temporal variability of chip workload, cause lateral and vertical temperature non-uniformities (variations) in the chip structure. The assumption of an uniform temperature for a large circuit leads to inaccurate determination of key design parameters. To improve design quality, we need precise estimation of temperature at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis of the designs needs to be done at multiple levels of granularity. To further investigate the flow of chip/package thermal analysis we exploit the Intel Single Chip Cloud Computer (SCC) and propose a methodology for calibration of SCC on-die temperature sensors. We also develop an infrastructure for online monitoring of SCC temperature sensor readings and SCC power consumption. Having the thermal simulation tool in hand, we propose MiMAPT, an approach for analyzing delay, power and temperature in digital integrated circuits. MiMAPT integrates seamlessly into industrial Front-end and Back-end chip design flows. It accounts for temperature non-uniformities and self-heating while performing analysis. Furthermore, we extend the temperature variation aware analysis of designs to 3D MPSoCs with Wide-I/O DRAM. We improve the DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting the per-DRAM-bank refresh period accordingly. We develop an advanced virtual platform which models the performance, power, and thermal behavior of a 3D-integrated MPSoC with Wide-I/O DRAMs in detail. Moving towards real-world multi-core heterogeneous SoC designs, a reconfigurable heterogeneous platform (ZYNQ) is exploited to further study the performance and energy efficiency of various CPU-accelerator data sharing methods in heterogeneous hardware architectures. A complete hardware accelerator featuring clusters of OpenRISC CPUs, with dynamic address remapping capability is built and verified on a real hardware.

Sistema interattivo di collaudo per moduli di lettura di codici ottici

Questa tesi descrive il progetto e lo sviluppo di un sistema informatico interattivo per il collaudo di moduli elettronici destinati alla lettura di codici ottici quali, ad esempio, codici a barre. Il componente principale di questo sistema interattivo è una cosiddetta interfaccia grafica con l'utente, attraverso la quale è possibile progettare passi di prova, prove e piani di prove nonchè controllare l'esecuzione del collaudo. I linguaggi di programmazione utilizzati sono C# e C++. Nella tesi vengono presentati vari diagrammi Unified Modeling Language (UML) del sistema informatico sviluppato. Nelle appendici vengono riportati un elenco esaustivo dei controlli grafici utilizzati, un elenco esaustivo degli eventi gestiti dall'interfaccia grafica e viene anche riportato, quasi integralmente, il codice sorgente sviluppato.

BYOD: Moving toward a More Mobile and Productive Workforce

In recent years there has been a personal and organizational trend toward mobility and the use of mobile technologies such as laptops, mobile phones and tablets. With this proliferation of devices, the desire to combine as many functions as possible into one device has also arisen. This concept is commonly called convergence. Generally, device convergence has been segmented between devices for work and devices for home use. Recently, however, the concept of Bring Your Own Device (BYOD) has emerged as organizations attempt to bridge the work/home divide in hopes of increasing employee productivity and reducing corporate technology costs. This paper examines BYOD projects at IBM, Cisco, Citrix, and Intel and then integrates this analysis with current literature to develop and present a BYOD Implementation Success model.

Córdoba ¿capital nacional de las tecnologías de la información y la comunicación o paraíso fiscal y de mano de obra calificada barata?

El discurso del gobierno de la provincia de Córdoba apuesta a una ciudad de las tecnologías. El modelo elegido privilegia el lugar de las empresas de software y los call centers, especialmente aquellos liderados por capitales extranjeros. A los fines de presentar algunos interrogantes sobre las políticas de promoción industrial, se tomarán como punto de partida los recientes anuncios del desembarco de Intel en Córdoba y se analizarán los beneficios ofrecidos por el gobierno. Además se indagará acerca de las ventajas y desventajas de favorecer la localización de estas empresas, y se ampliará el campo de estudio para incluir las empresas de capitales locales que participan en estas ramas productivas. De esta forma se busca iniciar un debate y reflexionar acerca del impacto del modelo adoptado por el gobierno provincial.

Córdoba ¿capital nacional de las tecnologías de la información y la comunicación o paraíso fiscal y de mano de obra calificada barata?

El discurso del gobierno de la provincia de Córdoba apuesta a una ciudad de las tecnologías. El modelo elegido privilegia el lugar de las empresas de software y los call centers, especialmente aquellos liderados por capitales extranjeros. A los fines de presentar algunos interrogantes sobre las políticas de promoción industrial, se tomarán como punto de partida los recientes anuncios del desembarco de Intel en Córdoba y se analizarán los beneficios ofrecidos por el gobierno. Además se indagará acerca de las ventajas y desventajas de favorecer la localización de estas empresas, y se ampliará el campo de estudio para incluir las empresas de capitales locales que participan en estas ramas productivas. De esta forma se busca iniciar un debate y reflexionar acerca del impacto del modelo adoptado por el gobierno provincial.

Córdoba ¿capital nacional de las tecnologías de la información y la comunicación o paraíso fiscal y de mano de obra calificada barata?

El discurso del gobierno de la provincia de Córdoba apuesta a una ciudad de las tecnologías. El modelo elegido privilegia el lugar de las empresas de software y los call centers, especialmente aquellos liderados por capitales extranjeros. A los fines de presentar algunos interrogantes sobre las políticas de promoción industrial, se tomarán como punto de partida los recientes anuncios del desembarco de Intel en Córdoba y se analizarán los beneficios ofrecidos por el gobierno. Además se indagará acerca de las ventajas y desventajas de favorecer la localización de estas empresas, y se ampliará el campo de estudio para incluir las empresas de capitales locales que participan en estas ramas productivas. De esta forma se busca iniciar un debate y reflexionar acerca del impacto del modelo adoptado por el gobierno provincial.