Silicon-Based Asymmetric Add-Drop Microring Resonators with Ultra-Large Through-Port Extinctions

We theoretically simulate and experimentally demonstrate ultra-large through-port extinctions in silicon-based asymmetrically-coupled add-drop microring resonators (MRs). Through-port responses in an add-drop MR are analyzed by simulations and large extinctions are found when the MR is near-critically coupled. Accurate fabrication techniques are applied in producing a series of 20 mu m-radii add-drop microrings with drop-side gap-widths in slight differences. A through-port extinction of about 42.7 dB is measured in an MR with through-and drop-side gap-width to be respectively 280 nm and 295 nm. The large extinction suggests about a 20.5 dB improvement from the symmetrical add-drop MR of the same size and the through-side gap-width. The experimental results are finally compared with the post-fabrication simulations, which show a gap-width tolerance of > 30 nm for the through-port extinction enhancement.

A 5GHz low power WLAN transceiver SiGe RFIC for personal communication terminal applications

A low-cost low-power single chip WLAN 802.11a transceiver is designed for personal communication terminal and local multimedia data transmission. It has less than 130mA current dissipation, maximal 67dB gain and can be programmed to be 20dB minimal gain. The receiver system noise figure is 6.4dB in hige-gain mode.

A novel low-power input-independent MOS AC/DC charge pump

This paper presents a novel fully integrated MOS AC to DC charge pump with low power dissipation and stable output for RFID applications. To improve the input sensitivity, we replaced Schottky-diodes in conventional charge pumps with MOS diodes with zero threshold, which has less process defects and is thus more compatible with other circuits. The charge pump in a RFID transponder is implemented in a 0.35um CMOS technology with 0.24 sq mm die size. The analytical model of the charge pump and the simulation results are presented.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.