Qualitative Analysis of MOS Circuits

With the push towards sub-micron technology, transistor models have become increasingly complex. The number of components in integrated circuits has forced designer's efforts and skills towards higher levels of design. This has created a gap between design expertise and the performance demands increasingly imposed by the technology. To alleviate this problem, software tools must be developed that provide the designer with expert advice on circuit performance and design. This requires a theory that links the intuitions of an expert circuit analyst with the corresponding principles of formal theory (i.e. algebra, calculus, feedback analysis, network theory, and electrodynamics), and that makes each underlying assumption explicit.

Optimization and finite element analysis for reliable electronic packaging

This paper demonstrates a modeling and design approach that couples computational mechanics techniques with numerical optimisation and statistical models for virtual prototyping and testing in different application areas concerning reliability of eletronic packages. The integrated software modules provide a design engineer in the electronic manufacturing sector with fast design and process solutions by optimizing key parameters and taking into account complexity of certain operational conditions. The integrated modeling framework is obtained by coupling the multi-phsyics finite element framework - PHYSICA - with the numerical optimisation tool - VisualDOC into a fully automated design tool for solutions of electronic packaging problems. Response Surface Modeling Methodolgy and Design of Experiments statistical tools plus numerical optimisaiton techniques are demonstrated as a part of the modeling framework. Two different problems are discussed and solved using the integrated numerical FEM-Optimisation tool. First, an example of thermal management of an electronic package on a board is illustrated. Location of the device is optimized to ensure reduced junction temperature and stress in the die subject to certain cooling air profile and other heat dissipating active components. In the second example thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and subsequently used to optimise the life-time of solder interconnects under thermal cycling.

Thermo-mechanical analysis of the packaging process for micro-electronic displays

Micro-electronic displays are sensitive devices and its performance is easily affected by external environmental factors. To enable the display to perform in extreme conditions, the device must be structurally strengthened, the effects of this packaging process was investigated. A thermo-mechanical finite element analysis was used to discover potential problems in the packaging process and to improve the overall design of the device. The main concern from the analysis predicted that displacement of the borosilicate glass and the Y stress of the adhesive are important. Using this information a design which reduced the variation of displacement and kept the stress to a minimum was suggested

Computer modelling analysis of the globtop's effects on aluminium wirebond reliability

In power electronics modules, heavy aluminium wires, i.e. wire diameters greater than 100 microns, are bonded to the active semiconductor devices and conductor metallization to form electric circuits of the power electronic module. Due to the high currents that may flow through these wires, a single connection usually contains several wires and thus, a large number of wires are used in a power electronics module. Under normal operation or test condition, a significant amount of stresses and strains induced in the wire and bonding interfaces, resulting in failure over time. In this paper, computer modelling techniques are used to analyse the effect of globtop design on the reliability of aluminium wirebonds under cyclic thermal-mechanical loading conditions. The results will show the sensitivity of the reliability of the wirebonds to the changes in the geometry and the material properties of the wirebond globtop.

Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Scaling issues for analogue circuits using Double Gate SOI transistors

This work presents a systematic analysis on the impact of source-drain engineering using gate

Design and analysis of dual-rail circuits for security applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC

Recently, two fast selective encryption methods for context-adaptive variable length coding and context-adaptive binary arithmetic coding in H.264/AVC were proposed by Shahid et al. In this paper, it was demonstrated that these two methods are not as efficient as only encrypting the sign bits of nonzero coefficients. Experimental results showed that without encrypting the sign bits of nonzero coefficients, these two methods can not provide a perceptual scrambling effect. If a much stronger scrambling effect is required, intra prediction modes, and the sign bits of motion vectors can be encrypted together with the sign bits of nonzero coefficients. For practical applications, the required encryption scheme should be customized according to a user's specified requirement on the perceptual scrambling effect and the computational cost. Thus, a tunable encryption scheme combining these three methods is proposed for H.264/AVC. To simplify its implementation and reduce the computational cost, a simple control mechanism is proposed to adjust the control factors. Experimental results show that this scheme can provide different scrambling levels by adjusting three control factors with no or very little impact on the compression performance. The proposed scheme can run in real-time and its computational cost is minimal. The security of the proposed scheme is also discussed. It is secure against the replacement attack when all three control factors are set to one.

Bit erasure analysis of binary adders in quantum-dot cellular automata

As a post-CMOS technology, the incipient Quantum-dot Cellular Automata technology has various advantages. A key aspect which makes it highly desirable is low power dissipation. One method that is used to analyse power dissipation in QCA circuits is bit erasure analysis. This method has been applied to analyse previously proposed QCA binary adders. However, a number of improved QCA adders have been proposed more recently that have only been evaluated in terms of area and speed. As the three key performance metrics for QCA circuits are speed, area and power, in this paper, a bit erasure analysis of these adders will be presented to determine their power dissipation. The adders to be analysed are the Carry Flow Adder (CFA), Brent-Kung Adder (B-K), Ladner-Fischer Adder (L-F) and a more recently developed area-delay efficient adder. This research will allow for a more comprehensive comparison between the different QCA adder proposals. To the best of the authors' knowledge, this is the first time power dissipation analysis has been carried out on these adders.

Communication Nonlinearities Techniques for Analysis of Passive Intermodulation

The X-parameter based nonlinear modelling tools have been adopted as the foundation for the advanced methodology
of experimental characterisation and design of passive nonlinear devices. Based upon the formalism of the Xparameters,
it provides a unified framework for co-design of antenna beamforming networks, filters, phase shifters and
other passive and active devices of RF front-end, taking into account the effect of their nonlinearities. The equivalent
circuits of the canonical elements are readily incorporated in the models, thus enabling evaluation of PIM effect on the
performance of individual devices and their assemblies. An important advantage of the presented methodology is its
compatibility with the industry-standard established commercial RF circuit simulator Agilent ADS.
The major challenge in practical implementation of the proposed approach is concerned with experimental retrieval of the X-parameters for canonical passive circuit elements. To our best knowledge commercial PIM testers and practical laboratory test instruments are inherently narrowband and do not allow for simultaneous vector measurements at the PIM and harmonic frequencies. Alternatively, existing nonlinear vector analysers (NVNA) support X-parameter measurements in a broad frequency bands with a range of stimuli, but their dynamic range is insufficient for the PIM characterisation in practical circuits. Further opportunities for adaptation of the X-parameters methodology to the PIM
characterisation of passive devices using the existing test instruments are explored.

Passive Intermodulation in Distributed Circuits with Cascaded Discrete Nonlinearities

The principle aspects of passive intermodulation (PIM) characterisation in distributed printed circuits with cascaded lumped nonlinearities are presented. Mechanisms of PIM generations have been investigated experimentally and modelled using the formalism of X-parameters. The devised equivalent circuit models are applied to the analysis of microstrip lines with distributed and cascaded lumped sources of nonlinearity. The dynamic measurements have revealed that PIM generation rates in straight and meandered microstrip lines differ and significantly deviate from those expected for the respective discrete sources of nonlinearity. The obtained results indicate that multiple physical sources of nonlinearity contribute to PIM generation in printed circuits. Finally, it is demonstrated that the electrical discontinuities can have significant effect on the overall PIM response of the distributed passive circuits and cause PIM product leakage and parasitic coupling between isolated circuit elements.

Heterogeneous error-resilient scheme for spectral analysis in ultra-low power wearable electrocardiogram devices

Wearable devices performing advanced bio-signal analysis algorithms are aimed to foster a revolution in healthcare provision of chronic cardiac diseases. In this context, energy efficiency is of paramount importance, as long-term monitoring must be ensured while relying on a tiny power source. Operating at a scaled supply voltage, just above the threshold voltage, effectively helps in saving substantial energy, but it makes circuits, and especially memories, more prone to errors, threatening the correct execution of algorithms. The use of error detection and correction codes may help to protect the entire memory content, however it incurs in large area and energy overheads which may not be compatible with the tight energy budgets of wearable systems. To cope with this challenge, in this paper we propose to limit the overhead of traditional schemes by selectively detecting and correcting errors only in data highly impacting the end-to-end quality of service of ultra-low power wearable electrocardiogram (ECG) devices. This partition adopts the protection of either significant words or significant bits of each data element, according to the application characteristics (statistical properties of the data in the application buffers), and its impact in determining the output. The proposed heterogeneous error protection scheme in real ECG signals allows substantial energy savings (11% in wearable devices) compared to state-of-the-art approaches, like ECC, in which the whole memory is protected against errors. At the same time, it also results in negligible output quality degradation in the evaluated power spectrum analysis application of ECG signals.