Silicide formation and the interaction of metals with polycrystalline Si

The main factors affecting solid-phase Si-metal interactions are reported in this work. The influence of the orientation of the Si substrates and the presence of impurities in metal films and at the Si-metal interface on the formation of nickel and chromium silicides have been demonstrated. We have observed that the formation and kinetic rate of growth of nickel silicides is strongly dependent on the orientation and crystallinity of the Si substrates; a fact which, up to date, has never been seriously investigated in silicide formation. Impurity contaminations in the Cr film and at the Si-Cr interface are the most dominant influencing factors in the formation and kinetic rate of growth of CrSi₂. The potentiality and use of silicides as a diffusion barrier in metallization on silicon devices were also investigated.

Two phases, Ni₂Si and NiSi, form simultaneously in two distinct sublayers in the reaction of Ni with amorphous Si, while only the former phase was observed on other substrates. On (111) oriented Si substrates the growth rate is about 2 to 3 times less than that on <100> or polycrystalline Si. Transmission electron micrographs establish-·that silicide layers grown on different substrates have different microcrystalline structures. The concept of grain-boundary diffusion is speculated to be an important factor in silicide formation.

The composition and kinetic rate of CrSi₂ formation are not influenced by the underlying Si substrate. While the orientation of the Si substrate does not affect the formation of CrSi₂ , the purity of the Cr film and the state of Si-Cr interface become the predominant factors in the reaction process. With an interposed layer of Pd₂Si between the Cr film and the Si substrate, CrSi₂ starts to form at a much lower temperature (400°C) relative to the Si-Cr system. However, the growth rate of CrSi₂ is observed to be independent of the thickness of the Pd2Si layer. For both Si-Cr and Si-Pd₂Si-Cr samples, the growth rate is linear with time with an activation energy of 1.7 ± 0.1 ev.

A tracer technique using radioactive ³¹Si (T_1/2 = 2.26 h) was used to study the formation of CrSi₂ on Pd₂Si. It is established from this experiment that the growth of CrSi₂ takes place partly by transport of Si directly from the Si substrate and partly by breaking Pd₂Si bonds, making free Si atoms available for the growth process.

The role of CrSi₂ in Pd-Al metallization on Si was studied. It is established that a thin CrSi₂ layer can be used as a diffusion barrier to prevent Al from interacting with Pd₂Si in the Pd-Al metallization on Si.

As a generalization of what has been observed for polycrystalline-Si-Al interaction, the reactions between polycrystalline Si (poly Si) and other metals were studied. The metals investigated include Ni, Cr, Pd, Ag and Au. For Ni, Cr and Pd, annealing results in silicide formation, at temperatures similar to those observed on single crystal Si substrates. For Al, Ag and Au, which form simple eutectics with Si annealing results in erosion of the poly Si layer and growth of Si crystallites in the metal films.

Backscattering spectrometry with 2.0 and 2.3 MeV ⁴He ions was the main analytical tool used in all our investigations. Other experimental techniques include the Read camera glancing angle x-ray diffraction, scanning electron, optical and transmission electron microscopy. Details of these analytical techniques are given in Chapter II.

Ni-silicide growth kinetics in Si and Si/SiO2 core/shell nanowires.

A systematic study of the kinetics of axial Ni silicidation of as-grown and oxidized Si nanowires (SiNWs) with different crystallographic orientations and core diameters ranging from ∼ 10 to 100 nm is presented. For temperatures between 300 and 440 °C the length of the total axial silicide intrusion varies with the square root of time, which provides clear evidence that the rate limiting step is diffusion of Ni through the growing silicide phase(s). A retardation of Ni-silicide formation for oxidized SiNWs is found, indicative of a stress induced lowering of the diffusion coefficients. Extrapolated growth constants indicate that the Ni flux through the silicided NW is dominated by surface diffusion, which is consistent with an inverse square root dependence of the silicide length on the NW diameter as observed for (111) orientated SiNWs. In situ TEM silicidation experiments show that NiSi(2) is the first forming phase for as-grown and oxidized SiNWs. The silicide-SiNW interface is thereby atomically abrupt and typically planar. Ni-rich silicide phases subsequently nucleate close to the Ni reservoir, which for as-grown SiNWs can lead to a complete channel break-off for prolonged silicidation due to significant volume expansion and morphological changes.

Taper-free and vertically oriented Ge nanowires on Ge/Si substrates grown by a two-temperature process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.

Defect-free GaAs/AlGaAs Core-shell nanowires on Si substrates

We report straight and vertically aligned defect-free GaAs nanowires grown on Si(111) substrates by metal-organic chemical vapor deposition. By deposition of thin GaAs buffer layers on Si substrates, these nanowires could be grown on the buffer layers with much less stringent conditions as otherwise imposed by epitaxy of III-V compounds on Si. Also, crystal-defect-free GaAs nanowires were grown by using either a two-temperature growth mode consisting of a short initial nucleation step under higher temperature followed by subsequent growth under lower temperature or a rapid growth rate mode with high source flow rate. These two growth modes not only eliminated planar crystallographic defects but also significantly reduced tapering. Core-shell GaAs-AlGaAs nanowires grown by the two-temperature growth mode showed improved optical properties with strong photoluminescence and long carrier life times. © 2011 American Chemical Society.

Structural and optical characterization of vertical GaAs/GaP core-shell nanowires grown on Si substrates

GaAs nanowires were grown on Si (111) substrates. By coating a thin GaAs buffer layer on Si surface and using a two-temperature growth, the morphology and crystal structure of GaAs nanowires were dramatically improved. The strained GaAs/GaP core-shell nanowires, based on the improved GaAs nanowires with a shell thickness of 25 nm, showed a significant shift in emission energy of 260 meV from the unstrained GaAs nanowires. © 2010 IEEE.

Novel growth and properties of GaAs nanowires on Si substrates.

Straight, vertically aligned GaAs nanowires were grown on Si(111) substrates coated with thin GaAs buffer layers. We find that the V/III precursor ratio and growth temperature are crucial factors influencing the morphology and quality of buffer layers. A double layer structure, consisting of a thin initial layer grown at low V/III ratio and low temperature followed by a layer grown at high V/III ratio and high temperature, is crucial for achieving straight, vertically aligned GaAs nanowires on Si(111) substrates. An in situ annealing step at high temperature after buffer layer growth improves the surface and structural properties of the buffer layer, which further improves the morphology of the GaAs nanowire growth. Through such optimizations we show that vertically aligned GaAs nanowires can be fabricated on Si(111) substrates and achieve the same structural and optical properties as GaAs nanowires grown directly on GaAs(111)B substrates.

Improvement of morphology, structure, and optical properties of GaAs nanowires grown on Si substrates

We investigate vertical and defect-free growth of GaAs nanowires on Si (111) substrates via a vapor-liquid-solid (VLS) growth mechanism with Au catalysts by metal-organic chemical vapor deposition (MOCVD). By using annealed thin GaAs buffer layers on the surface of Si substrates, most nanowires are grown on the substrates straight, following (111) direction; by using two temperature growth, the nanowires were grown free from structural defects, such as twin defects and stacking faults. Systematic experiments about buffer layers indicate that V/III ratio of precursor and growth temperature can affect the morphology and quality of the buffer layers. Especially, heterostructural buffer layers grown with different V/III ratios and temperatures and in-situ post-annealing step are very helpful to grow well arranged, vertical GaAs nanowires on Si substrates. The initial nanowires having some structural defects can be defect-free by two-temperature growth mode with improved optical property, which shows us positive possibility for optoelectronic device application. ©2010 IEEE.

Low-cost high-efficiency GaN LED on large-area si substrate

The use of large size Si substrates for epitaxy of nitride light emitting diode (LED) structures has attracted great interest because Si wafers are readily available in large diameter at low cost. In addition, such wafers are compatible with existing processing lines for the 6-inch and larger wafer sizes commonly used in the electronics industry. With the development of various methods to avoid wafer cracking and reduce the defect density, the performance of GaN-based LED and electronic devices has been greatly improved. In this paper, we review our methods of growing crack-free InGaN-GaN multiple quantum well (MQW) LED structures of high crystalline quality on Si(111) substrates. The performance of processed LED devices and its dependence on the threading dislocation density were studied. Full wafer-level LED processing using a conventional 6-inch III-V processing line is also presented, demonstrating the great advantage of using large-size Si substrates for mass production of GaN LED devices.

Study of GaN growth on ultra-thin Si membranes

10 mu m-thick ultra-thin Si (111) membranes for GaN epi-layers growth were successfully fabricated on silicon-on-insulator (SOI) substrate by backside etching the handle Si and buried oxide (BOX) layer. Then 1 mu m-thick GaN layers were deposited on these Si membranes by metal-organic chemical vapor deposition (MOCVD). The crack-free areas of 250 mu m, x 250 mu m were obtained on the GaN layers due to the reduction of thermal stress by using these ultra-thin Si membranes, which was further confirmed by the photoluminescence (PL) spectra and the simulation results from the finite element method calculation by using the software of ANSYS. In this paper, a newly developed approach was demonstrated to utilize micromechanical structures for GaN growth, which would improve the material quality of the epi-layers and facilitate GaN-based micro electro-mechanical system (MEMS) fabrication, especially the pressure sensor, in the future applications. (C) 2008 Elsevier Ltd. All rights reserved.

Influence of the rapid thermal annealing on the properties of thin a-Si films

The variation of the structure, morphology and the electrical properties of thin amorphous silicon films caused by Rapid Thermal Annealing is studied. The films annealed at 1200degreesC for 2 minutes change their structure to polycrystalline and as a result their resistivity decreases by 4 orders of magnitude. Due to the small thickness of the as deposited amorphous silicon the obtained poly-Si is strongly irregular and has many discontinuities in its texture.

Synthesis of GaN nanotip triangle pyramids on 3C-SiC epilayer/Si substrates via an in situ In-doping technique

GaN nanotip triangle pyramids were synthesized on 3C-SiC epilayer via an isoelectronic In-doping technique. The synthesis was carried out in a specially designed two-hot-boat chemical vapor deposition system. In (99.999%) and molten Ga (99.99%) with a mass ratio of about 1:4 were used as the source, and pieces of Si (111) wafer covered with 400-500 nm 3C-SiC epilayer were used as the substrates. The products were analyzed by x-ray diffraction, field emission scanning electron microscopy, high-resolution transmission electron microscopy, selected area electron diffraction, Raman spectroscopy, and photoluminescence measurements. Our results show that the as-synthesized GaN pyramids are perfect single crystal with wurtzite structure, which may have potential applications in electronic/photonic devices.

An improvement on Si-etching tetramethyl ammonium hydroxide solution

An optimal concentration of the etching solution for deep etching of silicon, including 3% tetramethyl ammonium hydroxide and 0.3% (NH4)(2)S2O8, was achieved in this paper. For this etching solution, the etching rates of silicon and silicon dioxide were about 1.1 mu m(.)min(-1) and 0.5 nm(.)min(-1), respectively. The etching ratio between (100) and (111) planes was about 34:1, and the etched surface was very smooth.

Comparison of the properties of GaN grown on complex Si-based structures

With the aim of investigating the possible integration of optoelectronic devices, epitaxial GaN layers have been grown on Si(Ill) semiconductor-on-insulator (SOI) and on Si/CoSi2/Si(111) using metalorganic chemical vapor deposition. The samples are found to possess a highly oriented wurtzite structure, a uniform thickness, and abrupt interfaces. The epitaxial orientation is determined as GaN(0001)//Si(111), GaN[1120]//Si[110], and GaN[1010]//Si[112], and the GaN layer is tensilely strained in the direction parallel to the interface. According to Rutherford backscattering/channeling spectrometry and (0002) rocking curves, the crystalline quality of GaN on Si(111) SOI is better than that of GaN on silicide. Room-temperature photoluminescence of GaN/SOI reveals a strong near-band-edge emission at 368 nm (3.37 eV) with a full width at half-maximum of 59 meV. (c) 2005 American Institute of Physics.

Effects of ZnO interlayers on thick GaN/Si film prepared by RF magnetron sputtering

We have successfully prepared a high-quality 2 mu m-thick GaN film with three inserted 30 nm-thick ZnO interlayers on Si (111) substrate without cracks by magnetron sputtering. The effects of the thickness and number of ZnO interlayers on the crystal quality of the GaN films were studied. It was found that the GaN crystal quality initially improved with the increase of the thickness of ZnO interlayers, but deteriorated quickly when the thickness exceeded 30 nm. Multiple ZnO interlayers were used as an effective means to further improve the crystal quality of the GaN film. By increasing the number of interlayers up to three, the cracks can be constrained to a certain extent, and the crystal quality of the GaN film greatly improved. (c) 2006 Elsevier B.V. All rights reserved.

Crack control in GaN grown on silicon (111) using In doped low-temperature AlGaN interlayer by metalorganic chemical vapor deposition

The effects of In doped low-temperature (LT) AlGaN interlayer on the properties of GaN/Si(111) by MOCVD have been investigated. Using In doping LT-interlayer can decrease the stress sufficiently for avoiding crack formation in a thick (2.0 mu m) GaN layer. Significant improvement in the crystal and optical properties of GaN layer is also achieved. In doping is observed to reduce the stress in AlGaN interlayer measured by high-resolution X-ray diffraction (HRXRD). It can provide more compressive stress to counteract tensile stress and reduce crack density in subsequent GaN layer. Moreover, as a surfactant, indium is observed to cause an enhanced PL intensity and the narrowed linewidths of PL and XRD spectra for the LT-interlayer. Additionally, the crystal quality of GaN layer is found to be dependent on the growth parameters of underneath In-doped LT-AlGaN interlayer. The optimal parameters, such as TMIn flow rate, TMAl flow rates and thickness, are achieved to obtain nearly 2.0 mu m thick crack free GaN film with advanced optical and crystal properties. (c) 2005 Elsevier B.V. All rights reserved.