SUPPLIER INVOLVEMENT IN NEW PRODUCT DEVELOPMENT: A CASE STUDY FROM THE SEMICONDUCTOR INDUSTRY

Global competition requires that the companies adapt themselves to technological changes rapidly, develop new products, reduce the cost, shorten the time to market, and increase the quality. In this context, supplier involvement in New Product Development (NPD) is determinant for a company to respond to the requirements of the increasingly dynamic markets. The main purpose of the paper is to demonstrate the importance of supplier involvement in NPD, buyer-supplier relationships and their effects on buyer’s NPD process, highlighting the benefits of supplier involvement, the barriers, the strategic aspects and industry aspects. These issues are addressed with a case study from the semiconductor industry. Besides helping to understand NPD in the semiconductor industry, the contribution and fi ndings of this work are clear: the results achieved confirm the findings of studies referred in the literature review, and confirm that the semiconductor industry sector requires a closer and more complex relationship structure with suppliers, given the specificities and challenges of the sector, such as rapid technological changes, permanent innovation, global competition, reduction of cost and time-to-market cycle, increased capacity, among other. The main contribution of the paper to the scientific literature and to managers is the better understanding of the buyer-supplier relationships in NPD in the semiconductor industry.

Laser scanning of active semiconductor devices--videotape script /

"This activity was supported by the Defense Advanced Research Projects Agency and the National Bureau of Standards."

Toward a national semiconductor strategy : second annual report of the National Advisory Committee on Semiconductors.

"February 1991."

Carrier momentum relaxation in highly doped polar semiconductors and semiconductor heterostructures

Highly doped polar semiconductors are essential components of today’s semiconductor industry. Most strikingly, transistors in modern electronic devices are polar semiconductor heterostructures. It is important to thoroughly understand carrier transport in such structures. In doped polar semiconductors, collective excitations of the carriers (plasmons) and the atoms (polar phonons) couple. These coupled collective excitations affect the electrical conductivity, here quantified through the carrier mobility. In scattering events, the carriers and the coupled collective modes transfer momentum between each other. Carrier momentum transferred to polar phonons can be lost to other phonons through anharmonic decay, resulting in a finite carrier mobility. The plasmons do not have a decay mechanism which transfers carrier momentum irretrievably. Hence, carrier-plasmon scattering results in infinite carrier mobility. Momentum relaxation due to either carrier–plasmon scattering or carrier–polar-phonon scattering alone are well understood. However, only this thesis manages to treat momentum relaxation due to both scattering mechanisms on an equal footing, enabling us to properly calculate the mobility limited by carrier–coupled plasmon–polar phonon scattering. We achieved this by solving the coupled Boltzmann equations for the carriers and the collective excitations, focusing on the “drag” term and on the anharmonic decay process of the collective modes. Our approach uses dielectric functions to describe both the carrier-collective mode scattering and the decay of the collective modes. We applied our method to bulk polar semiconductors and heterostructures where various polar dielectrics surround a semiconducting monolayer of MoS2, where taking plasmons into account can increase the mobility by up to a factor 15 for certain parameters. This screening effect is up to 85% higher than if calculated with previous methods. To conclude, our approach provides insight into the momentum relaxation mechanism for carrier–coupled collective mode scattering, and better tools for calculating the screened polar phonon and interface polar phonon limited mobility.

Caracterização do “warpage” e sua variabilidade no processo produtivo de encapsulamento de circuitos integrados

Nos últimos anos a indústria de semicondutores, nomeadamente a produção de memórias, tem sofrido uma grande evolução. A necessidade de baixar custos de produção, assim como de produzir sistemas mais complexos e com maior capacidade, levou à criação da tecnologia WLP (Wafer Level Packaging). Esta tecnologia permite a produção de sistemas mais pequenos, simplificar o fluxo do processo e providenciar uma redução significativa do custo final do produto. A WLP é uma tecnologia de encapsulamento de circuitos integrados quando ainda fazem parte de wafers (bolachas de silício), em contraste com o método tradicional em que os sistemas são individualizados previamente antes de serem encapsulados. Com o desenvolvimento desta tecnologia, surgiu a necessidade de melhor compreender o comportamento mecânico do mold compound (MC - polímero encapsulante) mais especificamente do warpage (empeno) de wafers moldadas. O warpage é uma característica deste produto e deve-se à diferença do coeficiente de expansão térmica entre o silício e o mold compound. Este problema é observável no produto através do arqueamento das wafers moldadas. O warpage de wafers moldadas tem grande impacto na manufatura. Dependendo da quantidade e orientação do warpage, o transporte, manipulação, bem como, a processamento das wafers podem tornar-se complicados ou mesmo impossíveis, o que se traduz numa redução de volume de produção e diminuição da qualidade do produto. Esta dissertação foi desenvolvida na Nanium S.A., empresa portuguesa líder mundial na tecnologia de WLP em wafers de 300mm e aborda a utilização da metodologia Taguchi, no estudo da variabilidade do processo de debond para o produto X. A escolha do processo e produto baseou-se numa análise estatística da variação e do impacto do warpage ao longo doprocesso produtivo. A metodologia Taguchi é uma metodologia de controlo de qualidade e permite uma aproximação sistemática num dado processo, combinando gráficos de controlo, controlo do processo/produto, e desenho do processo para alcançar um processo robusto. Os resultados deste método e a sua correta implementação permitem obter poupanças significativas nos processos com um impacto financeiro significativo. A realização deste projeto permitiu estudar e quantificar o warpage ao longo da linha de produção e minorar o impacto desta característica no processo de debond. Este projecto permitiu ainda a discussão e o alinhamento entre as diferentes áreas de produção no que toca ao controlo e a melhoria de processos. Conseguiu–se demonstrar que o método Taguchi é um método eficiente no que toca ao estudo da variabilidade de um processo e otimização de parâmetros. A sua aplicação ao processo de debond permitiu melhorar ou a fiabilidade do processo em termos de garantia da qualidade do produto, como ao nível do aumento de produção.

Intra-Task Device Scheduling for Real-Time Embedded Systems

An ever increasing need for extra functionality in a single embedded system demands for extra Input/Output (I/O) devices, which are usually connected externally and are expensive in terms of energy consumption. To reduce their energy consumption, these devices are equipped with power saving mechanisms. While I/O device scheduling for real-time (RT) systems with such power saving features has been studied in the past, the use of energy resources by these scheduling algorithms may be improved. Technology enhancements in the semiconductor industry have allowed the hardware vendors to reduce the device transition and energy overheads. The decrease in overhead of sleep transitions has opened new opportunities to further reduce the device energy consumption. In this research effort, we propose an intra-task device scheduling algorithm for real-time systems that wakes up a device on demand and reduces its active time while ensuring system schedulability. This intra-task device scheduling algorithm is extended for devices with multiple sleep states to further minimise the overall device energy consumption of the system. The proposed algorithms have less complexity when compared to the conservative inter-task device scheduling algorithms. The system model used relaxes some of the assumptions commonly made in the state-of-the-art that restrict their practical relevance. Apart from the aforementioned advantages, the proposed algorithms are shown to demonstrate the substantial energy savings.

Towards Certifiable Multicore-based Platforms for Avionics

Work in Progress Session, 21st IEEE Real-Time and Embedded Techonology and Applications Symposium (RTAS 2015). 13 to 16, Apr, 2015, pp 27-28. Seattle, U.S.A..

Towards the Certification of Multicore Platforms in the Avionics Domain

Poster presented in Work in Progress Session, The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 24 to 27, Mar, 2015. Porto, Portugal.

Towards the Certification of Multicore Platforms in the Avionics Domain

Presented at Work in Progress Session, The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 24 to 27, Mar, 2015. Porto, Portugal.

Estudo da qualidade de processos na fabricação de semicondutores

A indústria de semicondutores é um sector em permanente evolução tecnológica. A tendência de miniaturização e de otimização do espaço, a necessidade de produzir circuitos cada vez mais complexos, a tendência para o incremento do número de camadas em cada circuito integrado, são as condições necessárias para que a evolução tecnológica nesta área seja uma constante. Os processos ligados à produção de semicondutores estão também em permanente evolução, dada a pressão efetuada pelas necessidades acima expostas. Os equipamentos necessitam de uma crescente precisão, a qual tem que ser acompanhada de procedimentos rigorosos para que a qualidade atingida tenha sempre o patamar desejado. No entanto, a constante evolução nem sempre permite um adequado levantamento de todas as causas que estão na origem de alguns problemas detetados na fabricação de semicondutores. Este trabalho teve por objetivo efetuar um levantamento dos processos ligados ao fabrico de semicondutores a partir de uma pastilha de silício (wafer) previamente realizada, identificando para cada processo os possíveis defeitos introduzidos pelo mesmo, procurando inventariar as causas possíveis que possam estar na origem desse defeito e realizar procedimentos que permitam criar regras e procedimentos perfeitamente estabelecidos que permitam aprender com os erros e evitar que os mesmos problemas se possam vir a repetir em situações análogas em outros produtos de uma mesma família.

The joint R&D project: The case of the first Brazilian microcontroller chip

ABSTRACT The interorganizational cooperation, through joint efforts with various actors, allows the high-tech companies to complement resources, especially in R&D projects. Collaborative projects have been identified in many studies as an important strategy to produce complex products and services in uncertain and competitive environments. Thus, this research aims at deepening the understanding of how the development dynamics of a collaborative R&D project in an industry of high technology occur. In order to achieve the proposed objective, the R&D project of the first microcontroller in the Brazilian semiconductor industry was defined as the object of analysis. The empirical choice is justified by the uniqueness of the case, besides bringing a diversity of actors and a level of complementarity of resources that were significant to the success of the project. Given the motivation to know who the actors were and what the main forms of interorganizational coordination were used in this project, interviews were carried out and a questionnaire was also made, besides other documents related to the project. The results presented show a network of nine actors and their roles in the interorganizational collaboration process, as well as the forms of social and temporal overlapping, used in the coordination of collective efforts. Focusing on the mechanisms of temporal and social integration highlighted throughout the study, the inclusion of R&D projects in the typology for interorganizational projects is proposed in this paper, which was also proposed by Jones and Lichtenstein (2008).

A reusable smart interface for gas sensor resistance measurement

The advances of the semiconductor industry enable microelectromechanical systems sensors, signal conditioning logic and network access to be integrated into a smart sensor node. In this framework, a mixed-mode interface circuit for monolithically integrated gas sensor arrays was developed with high-level design techniques. This interface system includes analog electronics for inspection of up to four sensor arrays and digital logic for smart control and data communication. Although different design methodologies were used in the conception of the complete circuit, high-level synthesis tools and methodologies were crucial in speeding up the whole design cycle, enhancing reusability for future applications and producing a flexible and robust component.

Intelin, Toshiban ja Samsungin patenttipolitiikka 1990-luvun alusta lähtien

Tämä kandidaatintyö käsittelee puolijohdeteollisuusyritysten Intelin, Toshiban ja Samsungin patenttipolitiikkaa 1990-luvun alusta lähtien. Työn tarkoituksena on antaa vastauksia siihen, miksi patentointiaktiivisuudet (patenttiaineiston määrät) vaihtelevat niin suuresti yrityksestä toiseen saman alan sisällä. Yrityksiä tarkastellaan erityisesti kotimaidensa suhteen. Patentointiaktiivisuuden analyysissä käytetään IPC-luokittain jaoteltua patenttiaineistoa sekä patentointiin liittyviä artikkeleita ja kirjallisuutta. Yritysten sijainti ja paikallinen yrityskulttuuri vaikuttavat merkittävästi yritysten patenttipolitiikkaan. Vertailuyrityksillä on omat arvot ja toimintatavat, joilla patentointiin liittyviä asioita hoidetaan. Puolijohdeteollisuudessa ja yleisesti informaatioteknologiateollisuudessa, joissa käytetään paljon patentointia, on tärkeää, että maan johto suhtautuu positiivisesti immateriaalioikeuksiin. Kyseisen alan merkitys maiden hyvinvoinnille kasvaa koko ajan. Empiria-aineiston mukaan Intelin patentit ovat eteen- ja taaksepäin viittausten perusteella laadukkaimpia. 1990-luvulla Etelä-Korea panosti suuresti immateriaalioikeuksien kehittämiseen, mikä näkyy Samsungin patenttimäärän nousuna. Samsungilla on vertailuyrityksistä eniten patentteja, mutta ne ovat heikkolaatuisimpia. Toshiban patentit eivät saavuta määrällisesti Intelin taakse- ja eteenpäinviittauksia. Laadullisesti Toshiban patentit ovat kuitenkin parempia kuin Samsungin patentit. Kaikkiaan patentointi on lisääntynyt 1990-luvulla lähtien muun muassa parantuneen patenttisuojan ja helpottuneiden hakuprosessien ansiosta. Aasiassa on yleisempää käyttää strategista patentointia, muun muassa portfolion maksimointia. Yhdysvalloissa suhtaudutaan patentointiin enemmän taloudelliselta kannalta, kun taas puolestaan Aasiassa t&k-toiminta on pitkäjänteisempää.