Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

Visual front-end wars : Viola-Jones face detector vs Fourier Lucas-Kanade

The performance of visual speech recognition (VSR) systems are significantly influenced by the accuracy of the visual front-end. The current state-of-the-art VSR systems use off-the-shelf face detectors such as Viola- Jones (VJ) which has limited reliability for changes in illumination and head poses. For a VSR system to perform well under these conditions, an accurate visual front end is required. This is an important problem to be solved in many practical implementations of audio visual speech recognition systems, for example in automotive environments for an efficient human-vehicle computer interface. In this paper, we re-examine the current state-of-the-art VSR by comparing off-the-shelf face detectors with the recently developed Fourier Lucas-Kanade (FLK) image alignment technique. A variety of image alignment and visual speech recognition experiments are performed on a clean dataset as well as with a challenging automotive audio-visual speech dataset. Our results indicate that the FLK image alignment technique can significantly outperform off-the shelf face detectors, but requires frequent fine-tuning.

HFL micro inverter with front-end diode clamped multi-level inverter and half-wave cycloconverter

A high-frequency-link (HFL) micro inverter with a front-end diode clamped multi-level inverter and a grid-connected half-wave cycloconverter is proposed. The diode clamped multi-level inverter with an auxiliary capacitor is used to generate high-frequency (HF) three level quasi square-wave output and it is fed into a series resonant tank to obtain high frequency continuous sinusoidal current. The obtained continuous sinusoidal current is modulated by using the grid-connected half-wave cycloconverter to obtain grid synchronized output current in phase with the grid voltage. The phase shift power modulation is used with auxiliary capacitor at the front-end multi-level inverter to have soft-switching. The phase shift between the HFL resonant current and half-wave cycloconverter input voltage is modulated to obtain grid synchronized output current.

HFL PV micro-inverter with front-end current-fed converter and half-wave cycloconverter

A high-frequency-link micro inverter is proposed with a front-end dual inductor push-pull converter and a grid-connected half-wave cycloconverter. Pulse width modulation is used to control the front-end converter and phase shift modulation is used at the back-end converter to obtain grid synchronized output current. A series resonant circuit and high-frequency transformer are used to interface the front-end and the back-end converters. The operation of the proposed micro-inverter in grid-connected mode is validated using MATLAB/Simpower simulation. Experimental results are provided to further validate the operation.

Micro inverter with a front-end current-fed converter

The reliability of micro inverters is an important factor as it would be necessary to reduce cost and maintenance of the small and medium scale distributed PV power conversion systems. Electrolytic capacitors and active power decouple circuits can be avoided in micro inverters with the use of medium voltage DC-link. Such a DC-link based micro inverter is proposed with a front-end dual inductor current-fed push-pull converter. The primary side power switches of the front-end converter have reduced switching losses due to multi-resonant operation. In addition, the voltage and current stresses on the diodes of the secondary diode voltage doubler rectifier are reduced due to the presence of a series resonant circuit in the front-end converter. The operation of the proposed micro inverter is explained using an in-depth analysis of the switching characteristics of the power semiconductor devices. The theoretical analysis of the proposed micro inverter is validated using simulation result.

A Front end Switched Rectifier DC Source for Neutral Point Balancing of A NPC Three-Level Inverter for The Full Modulation Range

A switched DC voltage three level NPC is proposed in this paper to eliminate capacitor balancing problems in conventional three-level Neutral Point Clamped (NPC) inverter. The proposed configuration requires only one DC link with a voltage V-dc/2, where V-dc is the DC link voltage in a onventional NPC inverter. To get rated DC link voltage (V-dc), the voltage source is alternately onnected in parallel to one of the two series capacitors using two switches and two diodes with device voltage rating of V-dc/2. The frequency at which the voltage source is switched is independent and will not affect the operation of NPC inverter. The switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two level inverter in lower modulation range, thereby increases the reliability of the drive system. A space vector based PWM scheme is used to verify this proposed topology.

Neutral-point balancing of neutral-point-clamped three-level inverter with a front end switched rectifier DC source for the full modulationn range

A switched rectifier DC voltage source three-level neutral-point-clamped (NPC) converter topology is proposed here to alleviate the inverter from capacitor voltage balancing in three-level drive systems. The proposed configuration requires only one DC link with a voltage of half of that needed in a conventional NPC inverter. To obtain a rated DC link voltage, the rectifier DC source is alternately connected in parallel to one of the two series capacitors using two switches and two diodes with device voltage ratings of half the total DC bus voltage. The frequency at which the voltage source is switched is independent of the inverter and will not affect its operation since the switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two-level inverter in the lower modulation index range, thereby increasing the reliability of the drivesystem. A space-vector-based PWM scheme is used to verify this proposed topology on a laboratory system.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

A power scalable receiver front-end at 2.4 GHz

We propose a Low Noise Amplifier (LNA) architecture for power scalable receiver front end (FE) for Zigbee. The motivation for power scalable receiver is to enable minimum power operation while meeting the run-time performance needed. We use simple models to find empirical relations between the available signal and interference levels to come up with required Noise Figure (NF) and 3rd order Intermodulation Product (IIP3) numbers. The architecture has two independent digital knobs to control the NF and IIP3. Acceptable input match while using adaptation has been achieved by using an Active Inductor configuration for the source degeneration inductor of the LNA. The low IF receiver front end (LNA with I and Q mixers) was fabricated in 130nm RFCMOS process and tested.