High-coherence hybrid Si/III-V semiconductor lasers

The relentlessly increasing demand for network bandwidth, driven primarily by Internet-based services such as mobile computing, cloud storage and video-on-demand, calls for more efficient utilization of the available communication spectrum, as that afforded by the resurging DSP-powered coherent optical communications. Encoding information in the phase of the optical carrier, using multilevel phase modulationformats, and employing coherent detection at the receiver allows for enhanced spectral efficiency and thus enables increased network capacity. The distributed feedback semiconductor laser (DFB) has served as the near exclusive light source powering the fiber optic, long-haul network for over 30 years. The transition to coherent communication systems is pushing the DFB laser to the limits of its abilities. This is due to its limited temporal coherence that directly translates into the number of different phases that can be imparted to a single optical pulse and thus to the data capacity. Temporal coherence, most commonly quantified in the spectral linewidth Δν, is limited by phase noise, result of quantum-mandated spontaneous emission of photons due to random recombination of carriers in the active region of the laser.

In this work we develop a generically new type of semiconductor laser with the requisite coherence properties. We demonstrate electrically driven lasers characterized by a quantum noise-limited spectral linewidth as low as 18 kHz. This narrow linewidth is result of a fundamentally new laser design philosophy that separates the functions of photon generation and storage and is enabled by a hybrid Si/III-V integration platform. Photons generated in the active region of the III-V material are readily stored away in the low loss Si that hosts the bulk of the laser field, thereby enabling high-Q photon storage. The storage of a large number of coherent quanta acts as an optical flywheel, which by its inertia reduces the effect of the spontaneous emission-mandated phase perturbations on the laser field, while the enhanced photon lifetime effectively reduces the emission rate of incoherent quanta into the lasing mode. Narrow linewidths are obtained over a wavelength bandwidth spanning the entire optical communication C-band (1530-1575nm) at only a fraction of the input power required by conventional DFB lasers. The results presented in this thesis hold great promise for the large scale integration of lithographically tuned, high-coherence laser arrays for use in coherent communications, that will enable Tb/s-scale data capacities.

A fundamental approach to phase noise reduction in hybrid Si/III-V lasers

Spontaneous emission into the lasing mode fundamentally limits laser linewidths. Reducing cavity losses provides two benefits to linewidth: (1) fewer excited carriers are needed to reach threshold, resulting in less phase-corrupting spontaneous emission into the laser mode, and (2) more photons are stored in the laser cavity, such that each individual spontaneous emission event disturbs the phase of the field less. Strong optical absorption in III-V materials causes high losses, preventing currently-available semiconductor lasers from achieving ultra-narrow linewidths. This absorption is a natural consequence of the compromise between efficient electrical and efficient optical performance in a semiconductor laser. Some of the III-V layers must be heavily doped in order to funnel excited carriers into the active region, which has the side effect of making the material strongly absorbing.

This thesis presents a new technique, called modal engineering, to remove modal energy from the lossy region and store it in an adjacent low-loss material, thereby reducing overall optical absorption. A quantum mechanical analysis of modal engineering shows that modal gain and spontaneous emission rate into the laser mode are both proportional to the normalized intensity of that mode at the active region. If optical absorption near the active region dominates the total losses of the laser cavity, shifting modal energy from the lossy region to the low-loss region will reduce modal gain, total loss, and the spontaneous emission rate into the mode by the same factor, so that linewidth decreases while the threshold inversion remains constant. The total spontaneous emission rate into all other modes is unchanged.

Modal engineering is demonstrated using the Si/III-V platform, in which light is generated in the III-V material and stored in the low-loss silicon material. The silicon is patterned as a high-Q resonator to minimize all sources of loss. Fabricated lasers employing modal engineering to concentrate light in silicon demonstrate linewidths at least 5 times smaller than lasers without modal engineering at the same pump level above threshold, while maintaining the same thresholds.

Molecular Beam Epitaxial Growth of III-V Semiconductor Nanostructures on Silicon Substrates

The main focus and concerns of this PhD thesis is the growth of III-V semiconductor nanostructures (Quantum dots (QDs) and quantum dashes) on silicon substrates using molecular beam epitaxy (MBE) technique. The investigation of influence of the major growth parameters on their basic properties (density, geometry, composition, size etc.) and the systematic characterization of their structural and optical properties are the core of the research work. The monolithic integration of III-V optoelectronic devices with silicon electronic circuits could bring enormous prospect for the existing semiconductor technology. Our challenging approach is to combine the superior passive optical properties of silicon with the superior optical emission properties of III-V material by reducing the amount of III-V materials to the very limit of the active region. Different heteroepitaxial integration approaches have been investigated to overcome the materials issues between III-V and Si. However, this include the self-assembled growth of InAs and InGaAs QDs in silicon and GaAx matrices directly on flat silicon substrate, sitecontrolled growth of (GaAs/In0,15Ga0,85As/GaAs) QDs on pre-patterned Si substrate and the direct growth of GaP on Si using migration enhanced epitaxy (MEE) and MBE growth modes. An efficient ex-situ-buffered HF (BHF) and in-situ surface cleaning sequence based on atomic hydrogen (AH) cleaning at 500 °C combined with thermal oxide desorption within a temperature range of 700-900 °C has been established. The removal of oxide desorption was confirmed by semicircular streaky reflection high energy electron diffraction (RHEED) patterns indicating a 2D smooth surface construction prior to the MBE growth. The evolution of size, density and shape of the QDs are ex-situ characterized by atomic-force microscopy (AFM) and transmission electron microscopy (TEM). The InAs QDs density is strongly increased from 108 to 1011 cm-2 at V/III ratios in the range of 15-35 (beam equivalent pressure values). InAs QD formations are not observed at temperatures of 500 °C and above. Growth experiments on (111) substrates show orientation dependent QD formation behaviour. A significant shape and size transition with elongated InAs quantum dots and dashes has been observed on (111) orientation and at higher Indium-growth rate of 0.3 ML/s. The 2D strain mapping derived from high-resolution TEM of InAs QDs embedded in silicon matrix confirmed semi-coherent and fully relaxed QDs embedded in defectfree silicon matrix. The strain relaxation is released by dislocation loops exclusively localized along the InAs/Si interfaces and partial dislocations with stacking faults inside the InAs clusters. The site controlled growth of GaAs/In0,15Ga0,85As/GaAs nanostructures has been demonstrated for the first time with 1 μm spacing and very low nominal deposition thicknesses, directly on pre-patterned Si without the use of SiO2 mask. Thin planar GaP layer was successfully grown through migration enhanced epitaxy (MEE) to initiate a planar GaP wetting layer at the polar/non-polar interface, which work as a virtual GaP substrate, for the GaP-MBE subsequently growth on the GaP-MEE layer with total thickness of 50 nm. The best root mean square (RMS) roughness value was as good as 1.3 nm. However, these results are highly encouraging for the realization of III-V optical devices on silicon for potential applications.

Organic–inorganic bismuth (III)-based material: A lead-free, air-stable and solution-processable light-absorber beyond organolead perovskites

Methylammonium bismuth (III) iodide single crystals and films have been developed and investigated. We have further presented the first demonstration of using this organic–inorganic bismuth-based material to replace lead/tin-based perovskite materials in solution-processable solar cells. The organic–inorganic bismuth-based material has advantages of non-toxicity, ambient stability, and low-temperature solution-processability, which provides a promising solution to address the toxicity and stability challenges in organolead- and organotin-based perovskite solar cells. We also demonstrated that trivalent metal cation-based organic–inorganic hybrid materials can exhibit photovoltaic effect, which may inspire more research work on developing and applying organic-inorganic hybrid materials beyond divalent metal cations (Pb (II) and Sn (II)) for solar energy applications.

Growth and characterization of novel, III-V semiconductor heterostructures

The material presented in this thesis concerns the growth and characterization of III-V semiconductor heterostructures. Studies of the interactions between bound states in coupled quantum wells and between well and barrier bound states in AlAs/GaAs heterostructures are presented. We also demonstrate the broad array of novel tunnel structures realizable in the InAs/GaSb/AlSb material system. Because of the unique broken-gap band alignment of InAs/GaSb these structures involve transport between the conduction- and valence-bands of adjacent layers. These devices possess a wide range of electrical properties and are fundamentally different from conventional AlAs/GaAs tunnel devices. We report on the fabrication of a novel tunnel transistor with the largest reported room temperature current gains. We also present time-resolved studies of the growth fronts of InAs/GainSb strained layer superlattices and investigations of surface anion exchange reactions.

Chapter 2 covers tunneling studies of conventional AlAs/GaAs RTD's. The results of two studies are presented: (i) A test of coherent vs. sequential tunneling in triple barrier heterostructures, (ii) An optical measurement of the effect of barrier X-point states on Γ-point well states. In the first it was found if two quantum wells are separated by a sufficiently thin barrier, then the eigenstates of the system extend coherently across both wells and the central barriers. For thicker barriers between the wells, the electrons become localized in the individual wells and transport is best described by the electrons hopping between the wells. In the second, it was found that Γ-point well states and X-point barrier states interact strongly. The barrier X-point states modify the energies of the well states and increase the escape rate for carriers in the quantum well.

The results of several experimental studies of a novel class of tunnel devices realized in the InAs/GaSb/AlSb material system are presented in Chapter 3. These interband tunnel structures involve transport between conduction- and valence-band states in adjacent material layers. These devices are compared and contrasted with the conventional AlAs/GaAs structures discussed in Chapter 2 and experimental results are presented for both resonant and nonresonant devices. These results are compared with theoretical simulations and necessary extensions to the theoretical models are discussed.

In chapter 4 experimental results from a novel tunnel transistor are reported. The measured current gains in this transistor exceed 100 at room temperature. This is the highest reported gain at room temperature for any tunnel transistor. The device is analyzed and the current conduction and gain mechanisms are discussed.

Chapters 5 and 6 are studies of the growth of structures involving layers with different anions. Chapter 5 covers the growth of InAs/GainSb superlattices for far infrared detectors and time resolved, in-situ studies of their growth fronts. It was found that the bandgap of superlattices with identical layer thicknesses and compositions varied by as much as 40 meV depending on how their internal interfaces are formed. The absorption lengths in superlattices with identical bandgaps but whose interfaces were formed in different ways varied by as much as a factor of two. First the superlattice is discussed including an explanation of the device and the complications involved in its growth. The experimental technique of reflection high energy electron diffraction (RHEED) is reviewed, and the results of RHEED studies of the growth of these complicated structures are presented. The development of a time resolved, in-situ characterization of the internal interfaces of these superlattices is described. Chapter 6 describes the result of a detailed study of some of the phenomena described in chapter 5. X-ray photoelectron spectroscopy (XPS) studies of anion exchange reactions on the growth fronts of these superlattices are reported. Concurrent RHEED studies of the same physical systems studied with XPS are presented. Using the RHEED and XPS results, a real-time, indirect measurement of surface exchange reactions was developed.

Heteroepitaxy of Group IV and Group III-V semiconductor alloys for photovoltaic applications

Photovoltaic energy conversion represents a economically viable technology for realizing collection of the largest energy resource known to the Earth -- the sun. Energy conversion efficiency is the most leveraging factor in the price of energy derived from this process. This thesis focuses on two routes for high efficiency, low cost devices: first, to use Group IV semiconductor alloy wire array bottom cells and epitaxially grown Group III-V compound semiconductor alloy top cells in a tandem configuration, and second, GaP growth on planar Si for heterojunction and tandem cell applications.

Metal catalyzed vapor-liquid-solid grown microwire arrays are an intriguing alternative for wafer-free Si and SiGe materials which can be removed as flexible membranes. Selected area Cu-catalyzed vapor-liquid solid growth of SiGe microwires is achieved using chlorosilane and chlorogermane precursors. The composition can be tuned up to 12% Ge with a simultaneous decrease in the growth rate from 7 to 1 μm/min^-1. Significant changes to the morphology were observed, including tapering and faceting on the sidewalls and along the lengths of the wires. Characterization of axial and radial cross sections with transmission electron microscopy revealed no evidence of defects at facet corners and edges, and the tapering is shown to be due to in-situ removal of catalyst material during growth. X-ray diffraction and transmission electron microscopy reveal a Ge-rich crystal at the tip of the wires, strongly suggesting that the Ge incorporation is limited by the crystallization rate.

Tandem Ga_1-xIn_xP/Si microwire array solar cells are a route towards a high efficiency, low cost, flexible, wafer-free solar technology. Realizing tandem Group III-V compound semiconductor/Si wire array devices requires optimization of materials growth and device performance. GaP and Ga_1-xIn_xP layers were grown heteroepitaxially with metalorganic chemical vapor deposition on Si microwire array substrates. The layer morphology and crystalline quality have been studied with scanning electron microscopy and transmission electron microscopy, and they provide a baseline for the growth and characterization of a full device stack. Ultimately, the complexity of the substrates and the prevalence of defects resulted in material without detectable photoluminescence, unsuitable for optoelectronic applications.

Coupled full-field optical and device physics simulations of a Ga_0.51In_0.49P/Si wire array tandem are used to predict device performance. A 500 nm thick, highly doped "buffer" layer between the bottom cell and tunnel junction is assumed to harbor a high density of lattice mismatch and heteroepitaxial defects. Under simulated AM1.5G illumination, the device structure explored in this work has a simulated efficiency of 23.84% with realistic top cell SRH lifetimes and surface recombination velocities. The relative insensitivity to surface recombination is likely due to optical generation further away from the free surfaces and interfaces of the device structure.

Finally, GaP has been grown free of antiphase domains on Si (112) oriented substrates using metalorganic chemical vapor deposition. Low temperature pulsed nucleation is followed by high temperature continuous growth, yielding smooth, specular thin films. Atomic force microscopy topography mapping showed very smooth surfaces (4-6 Å RMS roughness) with small depressions in the surface. Thin films (~ 50 nm) were pseudomorphic, as confirmed by high resolution x-ray diffraction reciprocal space mapping, and 200 nm thick films showed full relaxation. Transmission electron microscopy showed no evidence of antiphase domain formation, but there is a population of microtwin and stacking fault defects.

Unexpected benefits of rapid growth rate for III-V nanowires.

In conventional planar growth of bulk III-V materials, a slow growth rate favors high crystallographic quality, optical quality, and purity of the resulting material. Surprisingly, we observe exactly the opposite effect for Au-assisted GaAs nanowire growth. By employing a rapid growth rate, the resulting nanowires are markedly less tapered, are free of planar crystallographic defects, and have very high purity with minimal intrinsic dopant incorporation. Importantly, carrier lifetimes are not adversely affected. These results reveal intriguing behavior in the growth of nanoscale materials, and represent a significant advance toward the rational growth of nanowires for device applications.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Arsenic(III,V) adsorption onto charred dolomite: charring optimization and batch studies

In this work, the removal of arsenic from aqueous solutions onto thermally processed dolomite is investigated. The dolomite was thermally processed (charred) at temperatures of 600, 700 and 800 degrees C for 1, 2, 4 and 8 h. Isotherm experiments were carried out on these samples over a wide pH range. A complete arsenic removal was achieved over the pH range studied when using the 800 degrees C charred dolomite. However, at this temperature, thermal degradation of the dolomite weakens its structure due to the decomposition of the magnesium carbonate, leading to a partial dissolution. For this reason, the dolomitic sorbent chosen for further investigations was the 8 h at 700 degrees C material. Isotherm studies indicated that the Langmuir model was successful in describing the process to a better extent than the Freundlich model for the As(V) adsorption on the selected charred dolomite. However, for the As(III) adsorption, the Freundlich model was more successful in describing the process. The maximum adsorption capacities of charred dolomite for arsenite and arsenate ions are 1.846 and 2.157 mg/g, respectively. It was found that both the pseudo first- and second-order kinetic models are able to describe the experimental data (R-2 > 0.980). The data suggest the charring process allows dissociation of the dolomite to calcium carbonate and magnesium oxide, which accelerates the process of arsenic oxide and arsenic carbonate precipitation. (C) 2014 Elsevier B.V. All rights reserved.

Effects of internal luminescence and internal optics on V-oc and J(sc) of III-V solar cells

For solar cells dominated by radiative recombination, the performance can be significantly enhanced by improving the internal optics. Internally radiated photons can be directly emitted from the cell, but if confined by good internal reflectors at the front and back of the cell they can also be re-absorbed with a significant probability. This so-called photon recycling leads to an increase in the equilibrium minority carrier concentration and therefore the open-circuit voltage, Voc. In multijunction cells, the internal luminescence from a particular junction can also be coupled into a lower bandgap junction where it generates photocurrent in addition to the externally generated photocurrent, and affects the overall performance of the tandem. We demonstrate and discuss the implications of a detailed model that we have developed for real, non-idealized solar cells that calculates the external luminescent efficiency, accounting for wavelength-dependent optical properties in each layer, parasitic optical and electrical losses, multiple reflections within the cell and isotropic internal emission. The calculation leads to Voc, and we show data on high quality GaAs cells that agree with the trends in the model as the optics are systematically varied. For multijunction cells the calculation also leads to the luminescent coupling efficiency, and we show data on GaInP/GaAs tandems where the trends also agree as the coupling is systematically varied. In both cases, the effects of the optics are most prominent in cells with good material quality. The model is applicable to any solar cell for which the optical properties of each layer are well-characterized, and can be used to explore a wide phase space of design for single junction and multijunction solar cells.

In-situ and Ex-situ characterization of III-V semiconductor materials and solar cells upon 10 MEV proton irradiation

In this work we present the results and analysis of a 10 MeV proton irradiation experiment performed on III-V semiconductor materials and solar cells. A set of representative devices including lattice-matched InGaP/GaInAs/Ge triple junction solar cells and single junction GaAs and InGaP component solar cells and a Ge diode were irradiated for different doses. The devices were studied in-situ before and after each exposure at dark and 1 sun AM0 illumination conditions, using a solar simulator connected to the irradiation chamber through a borosilicate glass window. Ex-situ characterization techniques included dark and 1 sun AM0 illumination I-V measurements. Furthermore, numerical simulation of the devices using D-AMPS-1D code together with calculations based on the TRIM software were performed in order to gain physical insight on the experimental results. The experiment also included the proton irradiation of an unprocessed Ge solar cell structure as well as the irradiation of a bare Ge(100) substrate. Ex-situ material characterization, after radioactive deactivation of the samples, includes Raman spectroscopy and spectral reflectivity.

MOVPE growth of III-V semiconductors on silicon for third generation solar cells

Esta Tesis trata sobre el desarrollo y crecimiento -mediante tecnología MOVPE (del inglés: MetalOrganic Vapor Phase Epitaxy)- de células solares híbridas de semiconductores III-V sobre substratos de silicio. Esta integración pretende ofrecer una alternativa a las células actuales de III-V, que, si bien ostentan el récord de eficiencia en dispositivos fotovoltaicos, su coste es, a día de hoy, demasiado elevado para ser económicamente competitivo frente a las células convencionales de silicio. De este modo, este proyecto trata de conjugar el potencial de alta eficiencia ya demostrado por los semiconductores III-V en arquitecturas de células fotovoltaicas multiunión con el bajo coste, la disponibilidad y la abundancia del silicio. La integración de semiconductores III-V sobre substratos de silicio puede afrontarse a través de diferentes aproximaciones. En esta Tesis se ha optado por el desarrollo de células solares metamórficas de doble unión de GaAsP/Si. Mediante esta técnica, la transición entre los parámetros de red de ambos materiales se consigue por medio de la formación de defectos cristalográficos (mayoritariamente dislocaciones). La idea es confinar estos defectos durante el crecimiento de sucesivas capas graduales en composición para que la superficie final tenga, por un lado, una buena calidad estructural, y por otro, un parámetro de red adecuado. Numerosos grupos de investigación han dirigido sus esfuerzos en los últimos años en desarrollar una estructura similar a la que aquí proponemos. La mayoría de éstos se han centrado en entender los retos asociados al crecimiento de materiales III-V, con el fin de conseguir un material de alta calidad cristalográfica. Sin embargo, prácticamente ninguno de estos grupos ha prestado especial atención al desarrollo y optimización de la célula inferior de silicio, cuyo papel va a ser de gran relevancia en el funcionamiento de la célula completa. De esta forma, y con el fin de completar el trabajo hecho hasta el momento en el desarrollo de células de III-V sobre silicio, la presente Tesis se centra, fundamentalmente, en el diseño y optimización de la célula inferior de silicio, para extraer su máximo potencial. Este trabajo se ha estructurado en seis capítulos, ordenados de acuerdo al desarrollo natural de la célula inferior. Tras un capítulo de introducción al crecimiento de semiconductores III-V sobre Si, en el que se describen las diferentes alternativas para su integración; nos ocupamos de la parte experimental, comenzando con una extensa descripción y caracterización de los substratos de silicio. De este modo, en el Capítulo 2 se analizan con exhaustividad los diferentes tratamientos (tanto químicos como térmicos) que deben seguir éstos para garantizar una superficie óptima sobre la que crecer epitaxialmente el resto de la estructura. Ya centrados en el diseño de la célula inferior, el Capítulo 3 aborda la formación de la unión p-n. En primer lugar se analiza qué configuración de emisor (en términos de dopaje y espesor) es la más adecuada para sacar el máximo rendimiento de la célula inferior. En este primer estudio se compara entre las diferentes alternativas existentes para la creación del emisor, evaluando las ventajas e inconvenientes que cada aproximación ofrece frente al resto. Tras ello, se presenta un modelo teórico capaz de simular el proceso de difusión de fosforo en silicio en un entorno MOVPE por medio del software Silvaco. Mediante este modelo teórico podemos determinar qué condiciones experimentales son necesarias para conseguir un emisor con el diseño seleccionado. Finalmente, estos modelos serán validados y constatados experimentalmente mediante la caracterización por técnicas analíticas (i.e. ECV o SIMS) de uniones p-n con emisores difundidos. Uno de los principales problemas asociados a la formación del emisor por difusión de fósforo, es la degradación superficial del substrato como consecuencia de su exposición a grandes concentraciones de fosfina (fuente de fósforo). En efecto, la rugosidad del silicio debe ser minuciosamente controlada, puesto que éste servirá de base para el posterior crecimiento epitaxial y por tanto debe presentar una superficie prístina para evitar una degradación morfológica y cristalográfica de las capas superiores. En este sentido, el Capítulo 4 incluye un análisis exhaustivo sobre la degradación morfológica de los substratos de silicio durante la formación del emisor. Además, se proponen diferentes alternativas para la recuperación de la superficie con el fin de conseguir rugosidades sub-nanométricas, que no comprometan la calidad del crecimiento epitaxial. Finalmente, a través de desarrollos teóricos, se establecerá una correlación entre la degradación morfológica (observada experimentalmente) con el perfil de difusión del fósforo en el silicio y por tanto, con las características del emisor. Una vez concluida la formación de la unión p-n propiamente dicha, se abordan los problemas relacionados con el crecimiento de la capa de nucleación de GaP. Por un lado, esta capa será la encargada de pasivar la subcélula de silicio, por lo que su crecimiento debe ser regular y homogéneo para que la superficie de silicio quede totalmente pasivada, de tal forma que la velocidad de recombinación superficial en la interfaz GaP/Si sea mínima. Por otro lado, su crecimiento debe ser tal que minimice la aparición de los defectos típicos de una heteroepitaxia de una capa polar sobre un substrato no polar -denominados dominios de antifase-. En el Capítulo 5 se exploran diferentes rutinas de nucleación, dentro del gran abanico de posibilidades existentes, para conseguir una capa de GaP con una buena calidad morfológica y estructural, que será analizada mediante diversas técnicas de caracterización microscópicas. La última parte de esta Tesis está dedicada al estudio de las propiedades fotovoltaicas de la célula inferior. En ella se analiza la evolución de los tiempos de vida de portadores minoritarios de la base durante dos etapas claves en el desarrollo de la estructura Ill-V/Si: la formación de la célula inferior y el crecimiento de las capas III-V. Este estudio se ha llevado a cabo en colaboración con la Universidad de Ohio, que cuentan con una gran experiencia en el crecimiento de materiales III-V sobre silicio. Esta tesis concluye destacando las conclusiones globales del trabajo realizado y proponiendo diversas líneas de trabajo a emprender en el futuro. ABSTRACT This thesis pursues the development and growth of hybrid solar cells -through Metal Organic Vapor Phase Epitaxy (MOVPE)- formed by III-V semiconductors on silicon substrates. This integration aims to provide an alternative to current III-V cells, which, despite hold the efficiency record for photovoltaic devices, their cost is, today, too high to be economically competitive to conventional silicon cells. Accordingly, the target of this project is to link the already demonstrated efficiency potential of III-V semiconductor multijunction solar cell architectures with the low cost and unconstrained availability of silicon substrates. Within the existing alternatives for the integration of III-V semiconductors on silicon substrates, this thesis is based on the metamorphic approach for the development of GaAsP/Si dual-junction solar cells. In this approach, the accommodation of the lattice mismatch is handle through the appearance of crystallographic defects (namely dislocations), which will be confined through the incorporation of a graded buffer layer. The resulting surface will have, on the one hand a good structural quality; and on the other hand the desired lattice parameter. Different research groups have been working in the last years in a structure similar to the one here described, being most of their efforts directed towards the optimization of the heteroepitaxial growth of III-V compounds on Si, with the primary goal of minimizing the appearance of crystal defects. However, none of these groups has paid much attention to the development and optimization of the bottom silicon cell, which, indeed, will play an important role on the overall solar cell performance. In this respect, the idea of this thesis is to complete the work done so far in this field by focusing on the design and optimization of the bottom silicon cell, to harness its efficiency. This work is divided into six chapters, organized according to the natural progress of the bottom cell development. After a brief introduction to the growth of III-V semiconductors on Si substrates, pointing out the different alternatives for their integration; we move to the experimental part, which is initiated by an extensive description and characterization of silicon substrates -the base of the III-V structure-. In this chapter, a comprehensive analysis of the different treatments (chemical and thermal) required for preparing silicon surfaces for subsequent epitaxial growth is presented. Next step on the development of the bottom cell is the formation of the p-n junction itself, which is faced in Chapter 3. Firstly, the optimization of the emitter configuration (in terms of doping and thickness) is handling by analytic models. This study includes a comparison between the different alternatives for the emitter formation, evaluating the advantages and disadvantages of each approach. After the theoretical design of the emitter, it is defined (through the modeling of the P-in-Si diffusion process) a practical parameter space for the experimental implementation of this emitter configuration. The characterization of these emitters through different analytical tools (i.e. ECV or SIMS) will validate and provide experimental support for the theoretical models. A side effect of the formation of the emitter by P diffusion is the roughening of the Si surface. Accordingly, once the p-n junction is formed, it is necessary to ensure that the Si surface is smooth enough and clean for subsequent phases. Indeed, the roughness of the Si must be carefully controlled since it will be the basis for the epitaxial growth. Accordingly, after quantifying (experimentally and by theoretical models) the impact of the phosphorus on the silicon surface morphology, different alternatives for the recovery of the surface are proposed in order to achieve a sub-nanometer roughness which does not endanger the quality of the incoming III-V layers. Moving a step further in the development of the Ill-V/Si structure implies to address the challenges associated to the GaP on Si nucleation. On the one hand, this layer will provide surface passivation to the emitter. In this sense, the growth of the III-V layer must be homogeneous and continuous so the Si emitter gets fully passivated, providing a minimal surface recombination velocity at the interface. On the other hand, the growth should be such that the appearance of typical defects related to the growth of a polar layer on a non-polar substrate is minimized. Chapter 5 includes an exhaustive study of the GaP on Si nucleation process, exploring different nucleation routines for achieving a high morphological and structural quality, which will be characterized by means of different microscopy techniques. Finally, an extensive study of the photovoltaic properties of the bottom cell and its evolution during key phases in the fabrication of a MOCVD-grown III-V-on-Si epitaxial structure (i.e. the formation of the bottom cell; and the growth of III-V layers) will be presented in the last part of this thesis. This study was conducted in collaboration with The Ohio State University, who has extensive experience in the growth of III-V materials on silicon. This thesis concludes by highlighting the overall conclusions of the presented work and proposing different lines of work to be undertaken in the future.

Growth and application of planar III-V semiconductor nanowires grown with MOCVD

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.

Growth and Characterization of III-V Semiconductor Materials for MOCVD Reactor Qualification and Process Control

Metalorganic chemical vapor deposition is examined as a technique for growing compound semiconductor structures. Material analysis techniques for characterizing the quality and properties of compound semiconductor material are explained and data from recent commissioning work on a newly installed reactor at the University of Illinois is presented.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.