Scaling geospatial searches in large spatial databases

Modern geographical databases, which are at the core of geographic information systems (GIS), store a rich set of aspatial attributes in addition to geographic data. Typically, aspatial information comes in textual and numeric format. Retrieving information constrained on spatial and aspatial data from geodatabases provides GIS users the ability to perform more interesting spatial analyses, and for applications to support composite location-aware searches; for example, in a real estate database: “Find the nearest homes for sale to my current location that have backyard and whose prices are between $50,000 and $80,000”. Efficient processing of such queries require combined indexing strategies of multiple types of data. Existing spatial query engines commonly apply a two-filter approach (spatial filter followed by nonspatial filter, or viceversa), which can incur large performance overheads. On the other hand, more recently, the amount of geolocation data has grown rapidly in databases due in part to advances in geolocation technologies (e.g., GPS-enabled smartphones) that allow users to associate location data to objects or events. The latter poses potential data ingestion challenges of large data volumes for practical GIS databases. In this dissertation, we first show how indexing spatial data with R-trees (a typical data pre-processing task) can be scaled in MapReduce—a widely-adopted parallel programming model for data intensive problems. The evaluation of our algorithms in a Hadoop cluster showed close to linear scalability in building R-tree indexes. Subsequently, we develop efficient algorithms for processing spatial queries with aspatial conditions. Novel techniques for simultaneously indexing spatial with textual and numeric data are developed to that end. Experimental evaluations with real-world, large spatial datasets measured query response times within the sub-second range for most cases, and up to a few seconds for a small number of cases, which is reasonable for interactive applications. Overall, the previous results show that the MapReduce parallel model is suitable for indexing tasks in spatial databases, and the adequate combination of spatial and aspatial attribute indexes can attain acceptable response times for interactive spatial queries with constraints on aspatial data.

Time orientation in organizations: Polychronicity and multitasking

This dissertation consists of four studies examining two constructs related to time orientation in organizations: polychronicity and multitasking. The first study investigates the internal structure of polychronicity and its external correlates in a sample of undergraduate students (N = 732). Results converge to support a one-factor model and finds measures of polychronicity to be significantly related to extraversion, agreeableness, and openness to experience. The second study quantitatively reviews the existing research examining the relationship between polychronicity and the Big Five factors of personality. Results reveal a significant relationship between extraversion and openness to experience across studies. Studies three and four examine the usefulness of multitasking ability in the prediction of work related criteria using two organizational samples (N = 175 and 119, respectively). Multitasking ability demonstrated predictive validity, however the incremental validity over that of traditional predictors (i.e., cognitive ability and the Big Five factors of personality) was minimal. The relationships between multitasking ability, polychronicity, and other individual differences were also investigated. Polychronicity and multitasking ability proved to be distinct constructs demonstrating differential relationships with cognitive ability, personality, and performance. Results provided support for multitasking performance as a mediator in the relationship between multitasking ability and overall job performance. Additionally, polychronicity moderated the relationship between multitasking ability and both ratings of multitasking performance and overall job performance in Study four. Clarification of the factor structure of polychronicity and its correlates will facilitate future research in the time orientation literature. Results from two organizational samples point to work related measures of multitasking ability as a worthwhile tool for predicting the performance of job applicants.

System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Time Orientation in Organizations: Polychronicity and Multitasking

This dissertation consists of four studies examining two constructs related to time orientation in organizations: polychronicity and multitasking. The first study investigates the internal structure of polychronicity and its external correlates in a sample of undergraduate students (N = 732). Results converge to support a one-factor model and finds measures of polychronicity to be significantly related to extraversion, agreeableness, and openness to experience. The second study quantitatively reviews the existing research examining the relationship between polychronicity and the Big Five factors of personality. Results reveal a significant relationship between extraversion and openness to experience across studies. Studies three and four examine the usefulness of multitasking ability in the prediction of work related criteria using two organizational samples (N = 175 and 119, respectively). Multitasking ability demonstrated predictive validity, however the incremental validity over that of traditional predictors (i.e., cognitive ability and the Big Five factors of personality) was minimal. The relationships between multitasking ability, polychronicity, and other individual differences were also investigated. Polychronicity and multitasking ability proved to be distinct constructs demonstrating differential relationships with cognitive ability, personality, and performance. Results provided support for multitasking performance as a mediator in the relationship between multitasking ability and overall job performance. Additionally, polychronicity moderated the relationship between multitasking ability and both ratings of multitasking performance and overall job performance in Study four. Clarification of the factor structure of polychronicity and its correlates will facilitate future research in the time orientation literature. Results from two organizational samples point to work related measures of multitasking ability as a worthwhile tool for predicting the performance of job applicants.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.