Parallel-recusive filter structures for the computation of discrete transforms

A general approach is presented for implementing discrete transforms as a set of first-order or second-order recursive digital filters. Clenshaw's recurrence formulae are used to formulate the second-order filters. The resulting structure is suitable for efficient implementation of discrete transforms in VLSI or FPGA circuits. The general approach is applied to the discrete Legendre transform as an illustration.

Numerical Computation of a Certain Dirichlet Series Attached to Siegel Modular Forms of Degree Two

The Rankin convolution type Dirichlet series D-F,D-G(s) of Siegel modular forms F and G of degree two, which was introduced by Kohnen and the second author, is computed numerically for various F and G. In particular, we prove that the series D-F,D-G(s), which shares the same functional equation and analytic behavior with the spinor L-functions of eigenforms of the same weight are not linear combinations of those. In order to conduct these experiments a numerical method to compute the Petersson scalar products of Jacobi Forms is developed and discussed in detail.

Efficient computation of discrete polynomial transforms

This letter presents a new recursive method for computing discrete polynomial transforms. The method is shown for forward and inverse transforms of the Hermite, binomial, and Laguerre transforms. The recursive flow diagrams require only 2 additions, 2( +1) memory units, and +1multipliers for the +1-point Hermite and binomial transforms. The recursive flow diagram for the +1-point Laguerre transform requires 2 additions, 2( +1) memory units, and 2( +1) multipliers. The transform computation time for all of these transforms is ( )

Computation of discrete cosine transform using Clenshaw's recurence formula

Clenshaw’s recurrenee formula is used to derive recursive algorithms for the discrete cosine transform @CT) and the inverse discrete cosine transform (IDCT). The recursive DCT algorithm presented here requires one fewer delay element per coefficient and one fewer multiply operation per coeflident compared with two recently proposed methods. Clenshaw’s recurrence formula provides a unified development for the recursive DCT and IDCT algorithms. The M v e al gorithms apply to arbitrary lengtb algorithms and are appropriate for VLSI implementation.

A Metric to Evaluate and Synthesize Distributed Compliant Mechanisms

Compliant mechanisms with evenly distributed stresses have better load-bearing ability and larger range of motion than mechanisms with compliance and stresses lumped at flexural hinges. In this paper, we present a metric to quantify how uniformly the strain energy of deformation and thus the stresses are distributed throughout the mechanism topology. The resulting metric is used to optimize cross-sections of conceptual compliant topologies leading to designs with maximal stress distribution. This optimization framework is demonstrated for both single-port mechanisms and single-input single-output mechanisms. It is observed that the optimized designs have lower stresses than their nonoptimized counterparts, which implies an ability for single-port mechanisms to store larger strain energy, and single-input single-output mechanisms to perform larger output work before failure.

Performance Modeling Of Reconfigurable Distributed Systems Based On The Opensparc Fpga Board And The Sirc Communication Framewor

This thesis explores system performance for reconfigurable distributed systems and provides an analytical model for determining throughput of theoretical systems based on the OpenSPARC FPGA Board and the SIRC Communication Framework. This model was developed by studying a small set of variables that together determine a system¿s throughput. The importance of this model is in assisting system designers to make decisions as to whether or not to commit to designing a reconfigurable distributed system based on the estimated performance and hardware costs. Because custom hardware design and distributed system design are both time consuming and costly, it is important for designers to make decisions regarding system feasibility early in the development cycle. Based on experimental data the model presented in this paper shows a close fit with less than 10% experimental error on average. The model is limited to a certain range of problems, but it can still be used given those limitations and also provides a foundation for further development of modeling reconfigurable distributed systems.

Design and Development of an FPGA-based Distributed Computing Processing Platform

This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using a distributed system of field-programmable gate array (FPGA) boards. The software framework providesusers with the ability to easily develop applications that exploit the processing power of FPGAs while the hardware core manager framework gives users the ability to configure and interact with multiple FPGA boards and/or hardware cores. This thesis describes the design and development of these frameworks and analyzes the performance of a system that was constructed using the frameworks. The performance analysis included measuring the effect of incorporating additional hardware components into the system and comparing the system to a software-only implementation. This work draws conclusions based on the provided results of the performance analysis and offers suggestions for future work.