Implementation of a non ground meta interpreter for defeasible logic

Human reasoning is a fascinating and complex cognitive process that can be applied in different research areas such as philosophy, psychology, laws and financial. Unfortunately, developing supporting software (to those different areas) able to cope such as complex reasoning it’s difficult and requires a suitable logic abstract formalism. In this thesis we aim to develop a program, that has the job to evaluate a theory (a set of rules) w.r.t. a Goal, and provide some results such as “The Goal is derivable from the KB5 (of the theory)”. In order to achieve this goal we need to analyse different logics and choose the one that best meets our needs. In logic, usually, we try to determine if a given conclusion is logically implied by a set of assumptions T (theory). However, when we deal with programming logic we need an efficient algorithm in order to find such implications. In this work we use a logic rather similar to human logic. Indeed, human reasoning requires an extension of the first order logic able to reach a conclusion depending on not definitely true6 premises belonging to a incomplete set of knowledge. Thus, we implemented a defeasible logic7 framework able to manipulate defeasible rules. Defeasible logic is a non-monotonic logic designed for efficient defeasible reasoning by Nute (see Chapter 2). Those kind of applications are useful in laws area especially if they offer an implementation of an argumentation framework that provides a formal modelling of game. Roughly speaking, let the theory is the set of laws, a keyclaim is the conclusion that one of the party wants to prove (and the other one wants to defeat) and adding dynamic assertion of rules, namely, facts putted forward by the parties, then, we can play an argumentative challenge between two players and decide if the conclusion is provable or not depending on the different strategies performed by the players. Implementing a game model requires one more meta-interpreter able to evaluate the defeasible logic framework; indeed, according to Göedel theorem (see on page 127), we cannot evaluate the meaning of a language using the tools provided by the language itself, but we need a meta-language able to manipulate the object language8. Thus, rather than a simple meta-interpreter, we propose a Meta-level containing different Meta-evaluators. The former has been explained above, the second one is needed to perform the game model, and the last one will be used to change game execution and tree derivation strategies.

Progetto e realizzazione di riferimenti in tensione simmetrici in tecnologia CMOS

La tesi tratta del progetto e della realizzazione di un riferimento in tensione simmetrico e stabile in temperatura, realizzato in tecnologia CMOS. Nella progettazione analogica ad alta precisione ha assunto sempre più importanza il problema della realizzazione di riferimenti in tensione stabili in temperatura. Nella maggior parte dei casi vengono presentati Bandgap, ovvero riferimenti in tensione che sfruttano l'andamento in temperatura dell'energy gap del silicio al fine di ottenere una tensione costante in un ampio range di temperatura. Tale architettura risulta utile nei sistemi ad alimentazione singola compresa fra 0 e Vdd essendo in grado di generare una singola tensione di riferimento del valore tipico di 1.2V. Nella tesi viene presentato un riferimento in tensione in grado di offrire le stesse prestazioni di un Bandgap per quanto riguarda la variazione in temperatura ma in grado di lavorare sia in sistemi ad alimentazione singola che ad alimentazione duale. Il circuito proposto e' in grado di generare due tensioni, simmetriche rispetto a un riferimento dato, del valore nominale di ±450mV. All'interno della tesi viene descritto il progetto di due diverse architetture, entrambe in grado di generare le tensioni con le specifiche richieste. Le due architetture sono poi state confrontate analizzando in particolare la stabilità in temperatura, la potenza dissipata, il PSRR (Power Supply Rejection Ratio) e la simmetria delle tensioni generate. Al termine dell'analisi è stato poi implementato su silicio il circuito che garantiva le prestazioni migliori. In sede di disegno del layout su silicio sono stati affrontati i problemi derivanti dall'adattamento dei componenti al fine di ottenere una maggiore insensibilità del circuito stesso alle incertezze legate al processo di realizzazione. Infine sono state effettuate le misurazioni attraverso una probe station a 4 sonde per verificare il corretto funzionamento del circuito e le sue prestazioni.

Super shell logic - [sush-ic] - progetto di un edificio per il tempo libero a Tokyo. Implicazioni tettoniche ed estetiche delle logiche monoscocca integrate e stress lines analysis in architettura.

Implicazioni tettoniche ed estetiche delle logiche monoscocca integrate e stress lines analysis in architettura.

Modeling multiple state electrostatically formed nanowire transistors

The present thesis work proposes a new physical equivalent circuit model for a recently proposed semiconductor transistor, a 2-drain MSET (Multiple State Electrostatically Formed Nanowire Transistor). It presents a new software-based experimental setup that has been developed for carrying out numerical simulations on the device and on equivalent circuits. As of 2015, we have already approached the scaling limits of the ubiquitous CMOS technology that has been in the forefront of mainstream technological advancement, so many researchers are exploring different ideas in the realm of electrical devices for logical applications, among them MSET transistors. The idea that underlies MSETs is that a single multiple-terminal device could replace many traditional transistors. In particular a 2-drain MSET is akin to a silicon multiplexer, consisting in a Junction FET with independent gates, but with a split drain, so that a voltage-controlled conductive path can connect either of the drains to the source. The first chapter of this work presents the theory of classical JFETs and its common equivalent circuit models. The physical model and its derivation are presented, the current state of equivalent circuits for the JFET is discussed. A physical model of a JFET with two independent gates has been developed, deriving it from previous results, and is presented at the end of the chapter. A review of the characteristics of MSET device is shown in chapter 2. In this chapter, the proposed physical model and its formulation are presented. A listing for the SPICE model was attached as an appendix at the end of this document. Chapter 3 concerns the results of the numerical simulations on the device. At first the research for a suitable geometry is discussed and then comparisons between results from finite-elements simulations and equivalent circuit runs are made. Where points of challenging divergence were found between the two numerical results, the relevant physical processes are discussed. In the fourth chapter the experimental setup is discussed. The GUI-based environments that allow to explore the four-dimensional solution space and to analyze the physical variables inside the device are described. It is shown how this software project has been structured to overcome technical challenges in structuring multiple simulations in sequence, and to provide for a flexible platform for future research in the field.