Excitonic processes in multifunctional organic semiconductors for application in organic-light emitting transistor

In this thesis, I report on a comprehensive study about the photo-physical properties both in solution and in solid-state of a new thiophene based material (2,2’-(2,2’-bithiophene-5,5’-diyl)bis(5-butyl-5H-thieno[2,3-c]pyrrole-4,6)-dione (T4DIM) which shows an ambipolar semiconducting behavior together with electroluminescence in single-layer OLET device architecture[14

Electrochemistry of polycyclic aromatic molecules for advanced carbon nanostructures: luminescence and transistor applications

Polycyclic aromatic hydrocarbons (PAHs) are a large class of π-conjugated organic molecules with fused aromatic rings, which can be considered as fragments of 2D-graphene and have been extensively studied for their unique optical and electronic properties. The aim of this study is to understand the complex electrochemical behaviour of planar, curved, and heteroatom doped polycyclic aromatic molecules, particularly focusing on the oxidative coupling of their radical cations and the electrochemically induced cyclodehydrogenation reactions. In the first part of this thesis, the class of PAHs and aromatic nanostructures are introduced, and the reactivity of electrogenerated species is discussed, focusing on the electrochemical approach for the synthesis of extended π-conjugated structures. Subsequently, the electrochemical properties and reactivity of electrogenerated radical ions of planar and curved polyaromatics are correlated to their structures. In the third chapter, electrochemical cyclodehydrogenation of hexaphenylbenzene is used to prepare self-assembled hexabenzocoronene, directly deposited on an interdigitated electrode, which was characterised as organic electrochemical transistor. In the fourth chapter, the electrochemical behaviour of a family of azapyrene derivatives has been carefully investigated together with the electrogenerated chemiluminescence (ECL), both by ion-annihilation and co-reactant methods. Two structural azapyrene isomers with different nitrogen positions are thoroughly discussed in terms of redox and ECL properties. Interestingly, the ECL of only one of them showed a double emission with excimer formation. A detailed mechanism is discussed for the ECL by co-reactant benzoyl peroxide, to rationalise the different ECL behaviours of the two isomers on the basis of their topologically modulated electronic properties. In conclusion, the different electrochemical behaviours of PAHs were shown, focussing on the chemical reactivity of the electrogenerated species and taking advantage of it for important processes spanning from unconventional synthesis methods for carbon nanostructures to the exploitation of self-assembled nanostructured systems in organic electronics, to novel organic emitters in ECL.

Mixed-domain simulation and hybrid wafer-level packaging of RF-MEMS devices for wireless applications

In questa tesi verranno trattati sia il problema della creazione di un ambiente di simulazione a domini fisici misti per dispositivi RF-MEMS, che la definizione di un processo di fabbricazione ad-hoc per il packaging e l’integrazione degli stessi. Riguardo al primo argomento, sarà mostrato nel dettaglio lo sviluppo di una libreria di modelli MEMS all’interno dell’ambiente di simulazione per circuiti integrati Cadence c . L’approccio scelto per la definizione del comportamento elettromeccanico dei MEMS è basato sul concetto di modellazione compatta (compact modeling). Questo significa che il comportamento fisico di ogni componente elementare della libreria è descritto per mezzo di un insieme limitato di punti (nodi) di interconnessione verso il mondo esterno. La libreria comprende componenti elementari, come travi flessibili, piatti rigidi sospesi e punti di ancoraggio, la cui opportuna interconnessione porta alla realizzazione di interi dispositivi (come interruttori e capacità variabili) da simulare in Cadence c . Tutti i modelli MEMS sono implementati per mezzo del linguaggio VerilogA c di tipo HDL (Hardware Description Language) che è supportato dal simulatore circuitale Spectre c . Sia il linguaggio VerilogA c che il simulatore Spectre c sono disponibili in ambiente Cadence c . L’ambiente di simulazione multidominio (ovvero elettromeccanico) così ottenuto permette di interfacciare i dispositivi MEMS con le librerie di componenti CMOS standard e di conseguenza la simulazione di blocchi funzionali misti RF-MEMS/CMOS. Come esempio, un VCO (Voltage Controlled Oscillator) in cui l’LC-tank è realizzato in tecnologia MEMS mentre la parte attiva con transistor MOS di libreria sarà simulato in Spectre c . Inoltre, nelle pagine successive verrà mostrata una soluzione tecnologica per la fabbricazione di un substrato protettivo (package) da applicare a dispositivi RF-MEMS basata su vie di interconnessione elettrica attraverso un wafer di Silicio. La soluzione di packaging prescelta rende possibili alcune tecniche per l’integrazione ibrida delle parti RF-MEMS e CMOS (hybrid packaging). Verranno inoltre messe in luce questioni riguardanti gli effetti parassiti (accoppiamenti capacitivi ed induttivi) introdotti dal package che influenzano le prestazioni RF dei dispositivi MEMS incapsulati. Nel dettaglio, tutti i gradi di libertà del processo tecnologico per l’ottenimento del package saranno ottimizzati per mezzo di un simulatore elettromagnetico (Ansoft HFSSTM) al fine di ridurre gli effetti parassiti introdotti dal substrato protettivo. Inoltre, risultati sperimentali raccolti da misure di strutture di test incapsulate verranno mostrati per validare, da un lato, il simulatore Ansoft HFSSTM e per dimostrate, dall’altro, la fattibilit`a della soluzione di packaging proposta. Aldilà dell’apparente debole legame tra i due argomenti sopra menzionati è possibile identificare un unico obiettivo. Da un lato questo è da ricercarsi nello sviluppo di un ambiente di simulazione unificato all’interno del quale il comportamento elettromeccanico dei dispositivi RF-MEMS possa essere studiato ed analizzato. All’interno di tale ambiente, l’influenza del package sul comportamento elettromagnetico degli RF-MEMS può essere tenuta in conto per mezzo di modelli a parametri concentrati (lumped elements) estratti da misure sperimentali e simulazioni agli Elementi Finiti (FEM) della parte di package. Infine, la possibilità offerta dall’ambiente Cadence c relativamente alla simulazione di dipositivi RF-MEMS interfacciati alla parte CMOS rende possibile l’analisi di blocchi funzionali ibridi RF-MEMS/CMOS completi.

Memory hierarchy and data communication in heterogeneous reconfigurable SoCs

The miniaturization race in the hardware industry aiming at continuous increasing of transistor density on a die does not bring respective application performance improvements any more. One of the most promising alternatives is to exploit a heterogeneous nature of common applications in hardware. Supported by reconfigurable computation, which has already proved its efficiency in accelerating data intensive applications, this concept promises a breakthrough in contemporary technology development. Memory organization in such heterogeneous reconfigurable architectures becomes very critical. Two primary aspects introduce a sophisticated trade-off. On the one hand, a memory subsystem should provide well organized distributed data structure and guarantee the required data bandwidth. On the other hand, it should hide the heterogeneous hardware structure from the end-user, in order to support feasible high-level programmability of the system. This thesis work explores the heterogeneous reconfigurable hardware architectures and presents possible solutions to cope the problem of memory organization and data structure. By the example of the MORPHEUS heterogeneous platform, the discussion follows the complete design cycle, starting from decision making and justification, until hardware realization. Particular emphasis is made on the methods to support high system performance, meet application requirements, and provide a user-friendly programmer interface. As a result, the research introduces a complete heterogeneous platform enhanced with a hierarchical memory organization, which copes with its task by means of separating computation from communication, providing reconfigurable engines with computation and configuration data, and unification of heterogeneous computational devices using local storage buffers. It is distinguished from the related solutions by distributed data-flow organization, specifically engineered mechanisms to operate with data on local domains, particular communication infrastructure based on Network-on-Chip, and thorough methods to prevent computation and communication stalls. In addition, a novel advanced technique to accelerate memory access was developed and implemented.

Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures

The scale down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as they struggle to sustain the increasing tight bandwidth and latency constraints that these systems demand. The most promising solution for the future chip interconnects are the Networks on Chip (NoC). NoCs are network composed by routers and channels used to inter- connect the different components installed on the single microchip. Examples of advanced processors based on NoC interconnects are the IBM Cell processor, composed by eight CPUs that is installed on the Sony Playstation III and the Intel Teraflops pro ject composed by 80 independent (simple) microprocessors. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider and more heterogeneous world of Systems on Chip (SoC). SoC comprehend all the electronic devices that surround us such as cell-phones, smart-phones, house embedded systems, automotive systems, set-top boxes etc... SoC manufacturers such as ST Microelectronics , Samsung, Philips and also Universities such as Bologna University, M.I.T., Berkeley and more are all proposing proprietary frameworks based on NoC interconnects. These frameworks help engineers in the switch of design methodology and speed up the development of new NoC-based systems on chip. In this Thesis we propose an introduction of CMP and SoC interconnection networks. Then focusing on SoC systems we propose: • a detailed analysis based on simulation of the Spidergon NoC, a ST Microelectronics solution for SoC interconnects. The Spidergon NoC differs from many classical solutions inherited from the parallel computing world. Here we propose a detailed analysis of this NoC topology and routing algorithms. Furthermore we propose aEqualized a new routing algorithm designed to optimize the use of the resources of the network while also increasing its performance; • a methodology flow based on modified publicly available tools that combined can be used to design, model and analyze any kind of System on Chip; • a detailed analysis of a ST Microelectronics-proprietary transport-level protocol that the author of this Thesis helped developing; • a simulation-based comprehensive comparison of different network interface designs proposed by the author and the researchers at AST lab, in order to integrate shared-memory and message-passing based components on a single System on Chip; • a powerful and flexible solution to address the time closure exception issue in the design of synchronous Networks on Chip. Our solution is based on relay stations repeaters and allows to reduce the power and area demands of NoC interconnects while also reducing its buffer needs; • a solution to simplify the design of the NoC by also increasing their performance and reducing their power and area consumption. We propose to replace complex and slow virtual channel-based routers with multiple and flexible small Multi Plane ones. This solution allows us to reduce the area and power dissipation of any NoC while also increasing its performance especially when the resources are reduced. This Thesis has been written in collaboration with the Advanced System Technology laboratory in Grenoble France, and the Computer Science Department at Columbia University in the city of New York.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Design methodologies of microwawe integrated circuits for satellite telecommunications

The running innovation processes of the microwave transistor technologies, used in the implementation of microwave circuits, have to be supported by the study and development of proper design methodologies which, depending on the applications, will fully exploit the technology potentialities. After the choice of the technology to be used in the particular application, the circuit designer has few degrees of freedom when carrying out his design; in the most cases, due to the technological constrains, all the foundries develop and provide customized processes optimized for a specific performance such as power, low-noise, linearity, broadband etc. For these reasons circuit design is always a “compromise”, an investigation for the best solution to reach a trade off between the desired performances. This approach becomes crucial in the design of microwave systems to be used in satellite applications; the tight space constraints impose to reach the best performances under proper electrical and thermal de-rated conditions, respect to the maximum ratings provided by the used technology, in order to ensure adequate levels of reliability. In particular this work is about one of the most critical components in the front-end of a satellite antenna, the High Power Amplifier (HPA). The HPA is the main power dissipation source and so the element which mostly engrave on space, weight and cost of telecommunication apparatus; it is clear from the above reasons that design strategies addressing optimization of power density, efficiency and reliability are of major concern. Many transactions and publications demonstrate different methods for the design of power amplifiers, highlighting the availability to obtain very good levels of output power, efficiency and gain. Starting from existing knowledge, the target of the research activities summarized in this dissertation was to develop a design methodology capable optimize power amplifier performances complying all the constraints imposed by the space applications, tacking into account the thermal behaviour in the same manner of the power and the efficiency. After a reminder of the existing theories about the power amplifier design, in the first section of this work, the effectiveness of the methodology based on the accurate control of the dynamic Load Line and her shaping will be described, explaining all steps in the design of two different kinds of high power amplifiers. Considering the trade-off between the main performances and reliability issues as the target of the design activity, we will demonstrate that the expected results could be obtained working on the characteristics of the Load Line at the intrinsic terminals of the selected active device. The methodology proposed in this first part is based on the assumption that designer has the availability of an accurate electrical model of the device; the variety of publications about this argument demonstrates that it is so difficult to carry out a CAD model capable to taking into account all the non-ideal phenomena which occur when the amplifier operates at such high frequency and power levels. For that, especially for the emerging technology of Gallium Nitride (GaN), in the second section a new approach for power amplifier design will be described, basing on the experimental characterization of the intrinsic Load Line by means of a low frequency high power measurements bench. Thanks to the possibility to develop my Ph.D. in an academic spin-off, MEC – Microwave Electronics for Communications, the results of this activity has been applied to important research programs requested by space agencies, with the aim support the technological transfer from universities to industrial world and to promote a science-based entrepreneurship. For these reasons the proposed design methodology will be explained basing on many experimental results.

Microfluidic device and interfacial transport: application to biomolecules and nanostructures

The aim of my dissertation is to provide new knowledge and applications of microfluidics in a variety of problems, from materials science, devices, and biomedicine, where the control on the fluid dynamics and the local concentration of the solutions containing the relevant molecules (either materials, precursors, or biomolecules) is crucial. The control of interfacial phenomena occurring in solutions at dierent length scales is compelling in nanotechnology for devising new sensors, molecular electronics devices, memories. Microfluidic devices were fabricated and integrated with organic electronics devices. The transduction involves the species in the solution which infills the transistor channel and confined by the microfluidic device. This device measures what happens on the surface, at few nanometers from the semiconductor channel. Soft-lithography was adopted to fabricate platinum electrodes, starting from platinum carbonyl precursor. I proposed a simple method to assemble these nanostructures in periodic arrays of microstripes, and form conductive electrodes with characteristic dimension of 600 nm. The conductivity of these sub-microwires is compared with the values reported in literature and bulk platinum. The process is suitable for fabricating thin conductive patterns for electronic devices or electrochemical cells, where the periodicity of the conductive pattern is comparable with the diusion length of the molecules in solution. The ordering induced among artificial nanostructures is of particular interest in science. I show that large building blocks, like carbon nanotubes or core-shell nanoparticles, can be ordered and self-organised on a surface in patterns due to capillary forces. The eective probability of inducing order with microfluidic flow is modeled with finite element calculation on the real geometry of the microcapillaries, in soft-lithographic process. The oligomerization of A40 peptide in microconfined environment represents a new investigation of the extensively studied peptide aggregation. The added value of the approach I devised is the precise control on the local concentration of peptides together with the possibility to mimick cellular crowding. Four populations of oligomers where distinguished, with diameters ranging from 15 to 200 nm. These aggregates could not be addresses separately in fluorescence. The statistical analysis on the atomic force microscopy images together with a model of growth reveal new insights on the kinetics of amyloidogenesis as well as allows me to identify the minimum stable nucleus size. This is an important result owing to its implications in the understanding and early diagnosis and therapy of the Alzheimer’s disease

In situ real-time investigation of Organic Ultra-Thin-Film transistors: growth, electrical properties and biosensing applications

Organic electronics has grown enormously during the last decades driven by the encouraging results and the potentiality of these materials for allowing innovative applications, such as flexible-large-area displays, low-cost printable circuits, plastic solar cells and lab-on-a-chip devices. Moreover, their possible field of applications reaches from medicine, biotechnology, process control and environmental monitoring to defense and security requirements. However, a large number of questions regarding the mechanism of device operation remain unanswered. Along the most significant is the charge carrier transport in organic semiconductors, which is not yet well understood. Other example is the correlation between the morphology and the electrical response. Even if it is recognized that growth mode plays a crucial role into the performance of devices, it has not been exhaustively investigated. The main goal of this thesis was the finding of a correlation between growth modes, electrical properties and morphology in organic thin-film transistors (OTFTs). In order to study the thickness dependence of electrical performance in organic ultra-thin-film transistors, we have designed and developed a home-built experimental setup for performing real-time electrical monitoring and post-growth in situ electrical characterization techniques. We have grown pentacene TFTs under high vacuum conditions, varying systematically the deposition rate at a fixed room temperature. The drain source current IDS and the gate source current IGS were monitored in real-time; while a complete post-growth in situ electrical characterization was carried out. At the end, an ex situ morphological investigation was performed by using the atomic force microscope (AFM). In this work, we present the correlation for pentacene TFTs between growth conditions, Debye length and morphology (through the correlation length parameter). We have demonstrated that there is a layered charge carriers distribution, which is strongly dependent of the growth mode (i.e. rate deposition for a fixed temperature), leading to a variation of the conduction channel from 2 to 7 monolayers (MLs). We conciliate earlier reported results that were apparently contradictory. Our results made evident the necessity of reconsidering the concept of Debye length in a layered low-dimensional device. Additionally, we introduce by the first time a breakthrough technique. This technique makes evident the percolation of the first MLs on pentacene TFTs by monitoring the IGS in real-time, correlating morphological phenomena with the device electrical response. The present thesis is organized in the following five chapters. Chapter 1 makes an introduction to the organic electronics, illustrating the operation principle of TFTs. Chapter 2 presents the organic growth from theoretical and experimental points of view. The second part of this chapter presents the electrical characterization of OTFTs and the typical performance of pentacene devices is shown. In addition, we introduce a correcting technique for the reconstruction of measurements hampered by leakage current. In chapter 3, we describe in details the design and operation of our innovative home-built experimental setup for performing real-time and in situ electrical measurements. Some preliminary results and the breakthrough technique for correlating morphological and electrical changes are presented. Chapter 4 meets the most important results obtained in real-time and in situ conditions, which correlate growth conditions, electrical properties and morphology of pentacene TFTs. In chapter 5 we describe applicative experiments where the electrical performance of pentacene TFTs has been investigated in ambient conditions, in contact to water or aqueous solutions and, finally, in the detection of DNA concentration as label-free sensor, within the biosensing framework.

Advanced lithium and lithium-ion rechargeable batteries for automotive applications

The worldwide demand for a clean and low-fuel-consuming transport promotes the development of safe, high energy and power electrochemical storage and conversion systems. Lithium-ion batteries (LIBs) are considered today the best technology for this application as demonstrated by the recent interest of automotive industry in hybrid (HEV) and electric vehicles (EV) based on LIBs. This thesis work, starting from the synthesis and characterization of electrode materials and the use of non-conventional electrolytes, demonstrates that LIBs with novel and safe electrolytes and electrode materials meet the targets of specific energy and power established by U.S.A. Department of Energy (DOE) for automotive application in HEV and EV. In chapter 2 is reported the origin of all chemicals used, the description of the instruments used for synthesis and chemical-physical characterizations, the electrodes preparation, the batteries configuration and the electrochemical characterization procedure of electrodes and batteries. Since the electrolyte is the main critical point of a battery, in particular in large- format modules, in chapter 3 we focused on the characterization of innovative and safe electrolytes based on ionic liquids (characterized by high boiling/decomposition points, thermal and electrochemical stability and appreciable conductivity) and mixtures of ionic liquid with conventional electrolyte. In chapter 4 is discussed the microwave accelerated sol–gel synthesis of the carbon- coated lithium iron phosphate (LiFePO 4 -C), an excellent cathode material for LIBs thanks to its intrinsic safety and tolerance to abusive conditions, which showed excellent electrochemical performance in terms of specific capacity and stability. In chapter 5 are presented the chemical-physical and electrochemical characterizations of graphite and titanium-based anode materials in different electrolytes. We also characterized a new anodic material, amorphous SnCo alloy, synthetized with a nanowire morphology that showed to strongly enhance the electrochemical stability of the material during galvanostatic full charge/discharge cycling. Finally, in chapter 6, are reported different types of batteries, assembled using the LiFePO 4 -C cathode material, different anode materials and electrolytes, characterized by deep galvanostatic charge/discharge cycles at different C-rates and by test procedures of the DOE protocol for evaluating pulse power capability and available energy. First, we tested a battery with the innovative cathode material LiFePO 4 -C and conventional graphite anode and carbonate-based electrolyte (EC DMC LiPF 6 1M) that demonstrated to surpass easily the target for power-assist HEV application. Given that the big concern of conventional lithium-ion batteries is the flammability of highly volatile organic carbonate- based electrolytes, we made safe batteries with electrolytes based on ionic liquid (IL). In order to use graphite anode in IL electrolyte we added to the IL 10% w/w of vinylene carbonate (VC) that produces a stable SEI (solid electrolyte interphase) and prevents the graphite exfoliation phenomenon. Then we assembled batteries with LiFePO 4 -C cathode, graphite anode and PYR 14 TFSI 0.4m LiTFSI with 10% w/w of VC that overcame the DOE targets for HEV application and were stable for over 275 cycles. We also assembled and characterized ―high safety‖ batteries with electrolytes based on pure IL, PYR 14 TFSI with 0.4m LiTFSI as lithium salt, and on mixture of this IL and standard electrolyte (PYR 14 TFSI 50% w/w and EC DMC LiPF 6 50% w/w), using titanium-based anodes (TiO 2 and Li 4 Ti 5 O 12 ) that are commonly considered safer than graphite in abusive conditions. The batteries bearing the pure ionic liquid did not satisfy the targets for HEV application, but the batteries with Li 4 Ti 5 O 12 anode and 50-50 mixture electrolyte were able to surpass the targets. We also assembled and characterized a lithium battery (with lithium metal anode) with a polymeric electrolyte based on poly-ethilenoxide (PEO 20 – LiCF 3 SO 3 +10%ZrO 2 ), which satisfied the targets for EV application and showed a very impressive cycling stability. In conclusion, we developed three lithium-ion batteries of different chemistries that demonstrated to be suitable for application in power-assist hybrid vehicles: graphite/EC DMC LiPF 6 /LiFePO 4 -C, graphite/PYR 14 TFSI 0.4m LiTFSI with 10% VC/LiFePO 4 -C and Li 4 T i5 O 12 /PYR 14 TFSI 50%-EC DMC LiPF 6 50%/LiFePO 4 -C. We also demonstrated that an all solid-state polymer lithium battery as Li/PEO 20 –LiCF 3 SO 3 +10%ZrO 2 /LiFePO 4 -C is suitable for application on electric vehicles. Furthermore we developed a promising anodic material alternative to the graphite, based on SnCo amorphous alloy.

Organic heterostructure approach for multifunctional light-emitting field-effect transistors

The possibility of combining different functionalities in a single device is of great relevance for further development of organic electronics in integrated components and circuitry. Organic light-emitting transistors (OLETs) have been demonstrated to be able to combine in a single device the electrical switching functionality of a field-effect transistor and the capability of light generation. A novel strategy in OLET realization is the tri-layer vertical hetero-junction. This configuration is similar to the bi-layer except for the presence of a new middle layer between the two transport layers. This “recombination” layer presents high emission quantum efficiency and OLED-like (Organic Light-Emitting Diode) vertical bulk mobility value. The key idea of the vertical tri-layer hetero-junction approach in realizing OLETs is that each layer has to be optimized according to its specific function (charge transport, energy transfer, radiative exciton recombination). Clearly, matching the overall device characteristics with the functional properties of the single materials composing the active region of the OFET, is a great challenge that requires a deep investigation of the morphological, optical and electrical features of the system. As in the case of the bi-layer based OLETs, it is clear that the interfaces between the dielectric and the bottom transport layer and between the recombination and the top transport layer are crucial for guaranteeing good ambipolar field-effect electrical characteristics. Moreover interfaces between the bottom transport and the recombination layer and between the recombination and the top transport layer should provide the favourable conditions for the charge percolation to happen in the recombination layer and form excitons. Organic light emitting transistor based on the tri-layer approach with external quantum efficiency out-performing the OLED state of the art has been recently demonstrated [Capelli et al., Nat. Mater. 9 (2010) 496-503] widening the scientific and technological interest in this field of research.

Physical models for numerical simulation of Si-based nanoscale FETs and sensors

To continuously improve the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs), innovative device architectures, gate stack engineering and mobility enhancement techniques are under investigation. In this framework, new physics-based models for Technology Computer-Aided-Design (TCAD) simulation tools are needed to accurately predict the performance of upcoming nanoscale devices and to provide guidelines for their optimization. In this thesis, advanced physically-based mobility models for ultrathin body (UTB) devices with either planar or vertical architectures such as single-gate silicon-on-insulator (SOI) field-effect transistors (FETs), double-gate FETs, FinFETs and silicon nanowire FETs, integrating strain technology and high-κ gate stacks are presented. The effective mobility of the two-dimensional electron/hole gas in a UTB FETs channel is calculated taking into account its tensorial nature and the quantization effects. All the scattering events relevant for thin silicon films and for high-κ dielectrics and metal gates have been addressed and modeled for UTB FETs on differently oriented substrates. The effects of mechanical stress on (100) and (110) silicon band structures have been modeled for a generic stress configuration. Performance will also derive from heterogeneity, coming from the increasing diversity of functions integrated on complementary metal-oxide-semiconductor (CMOS) platforms. For example, new architectural concepts are of interest not only to extend the FET scaling process, but also to develop innovative sensor applications. Benefiting from properties like large surface-to-volume ratio and extreme sensitivity to surface modifications, silicon-nanowire-based sensors are gaining special attention in research. In this thesis, a comprehensive analysis of the physical effects playing a role in the detection of gas molecules is carried out by TCAD simulations combined with interface characterization techniques. The complex interaction of charge transport in silicon nanowires of different dimensions with interface trap states and remote charges is addressed to correctly reproduce experimental results of recently fabricated gas nanosensors.

Numerical study of graphene as a channel material for field-effect transistors

Graphene excellent properties make it a promising candidate for building future nanoelectronic devices. Nevertheless, the absence of an energy gap is an open problem for the transistor application. In this thesis, graphene nanoribbons and pattern-hydrogenated graphene, two alternatives for inducing an energy gap in graphene, are investigated by means of numerical simulations. A tight-binding NEGF code is developed for the simulation of GNR-FETs. To speed up the simulations, the non-parabolic effective mass model and the mode-space tight-binding method are developed. The code is used for simulation studies of both conventional and tunneling FETs. The simulations show the great potential of conventional narrow GNR-FETs, but highlight at the same time the leakage problems in the off-state due to various tunneling mechanisms. The leakage problems become more severe as the width of the devices is made larger, and thus the band gap smaller, resulting in a poor on/off current ratio. The tunneling FET architecture can partially solve these problems thanks to the improved subthreshold slope; however, it is also shown that edge roughness, unless well controlled, can have a detrimental effect in the off-state performance. In the second part of this thesis, pattern-hydrogenated graphene is simulated by means of a tight-binding model. A realistic model for patterned hydrogenation, including disorder, is developed. The model is validated by direct comparison of the momentum-energy resolved density of states with the experimental angle-resolved photoemission spectroscopy. The scaling of the energy gap and the localization length on the parameters defining the pattern geometry is also presented. The results suggest that a substantial transport gap can be attainable with experimentally achievable hydrogen concentration.

Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS

Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead. This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.